1 /* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
5 * Portions Copyright (c) 2007 Microsoft
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company may not be used to endorse or promote
17 * products derived from this software without specific prior written
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * ARMv6 assembly functions for manipulating caches.
33 * These routines can be used by any core that supports the mcrr address
41 #include <machine/asm.h>
46 * Functions to set the MMU Translation Table Base register
48 * We need to clean and flush the cache as it uses virtual
49 * addresses that are about to change.
52 #ifdef PMAP_CACHE_VIVT
53 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
54 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
56 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
58 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
60 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
68 /* LINTSTUB: void armv6_icache_sync_range(vaddr_t, vsize_t); */
69 ENTRY_NP(armv6_icache_sync_range)
72 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
73 mcrr p15, 0, r1, r0, c12 /* clean D cache range */
74 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
76 END(armv6_icache_sync_range)
78 /* LINTSTUB: void armv6_icache_sync_all(void); */
79 ENTRY_NP(armv6_icache_sync_all)
81 * We assume that the code here can never be out of sync with the
82 * dcache, so that we can safely flush the Icache and fall through
83 * into the Dcache cleaning code.
85 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
86 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
87 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
89 END(armv6_icache_sync_all)
91 /* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */
92 ENTRY(armv6_dcache_wb_range)
95 mcrr p15, 0, r1, r0, c12 /* clean D cache range */
96 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
98 END(armv6_dcache_wb_range)
100 /* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */
101 ENTRY(armv6_dcache_wbinv_range)
104 mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */
105 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
107 END(armv6_dcache_wbinv_range)
110 * Note, we must not invalidate everything. If the range is too big we
111 * must use wb-inv of the entire cache.
113 * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t);
115 ENTRY(armv6_dcache_inv_range)
118 mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */
119 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
121 END(armv6_dcache_inv_range)
123 /* LINTSTUB: void armv6_idcache_wbinv_range(vaddr_t, vsize_t); */
124 ENTRY(armv6_idcache_wbinv_range)
127 mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */
128 mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */
129 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
131 END(armv6_idcache_wbinv_range)
133 /* LINTSTUB: void armv6_idcache_wbinv_all(void); */
134 ENTRY_NP(armv6_idcache_wbinv_all)
136 * We assume that the code here can never be out of sync with the
137 * dcache, so that we can safely flush the Icache and fall through
138 * into the Dcache purging code.
140 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
141 /* Fall through to purge Dcache. */
143 /* LINTSTUB: void armv6_dcache_wbinv_all(void); */
144 ENTRY(armv6_dcache_wbinv_all)
145 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
146 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
148 END(armv6_idcache_wbinv_all)
149 END(armv6_dcache_wbinv_all)
151 ENTRY(armv6_idcache_inv_all)
153 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
155 END(armv6_idcache_inv_all)