2 * Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
3 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
6 * Developed by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of MARVELL nor the names of contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <machine/asm.h>
34 __FBSDID("$FreeBSD$");
36 #include <machine/sysreg.h>
42 .word _C_LABEL(arm_cache_loc)
44 .word _C_LABEL(arm_cache_type)
50 /* Based on algorithm from ARM Architecture Reference Manual */
51 ENTRY(armv7_dcache_wbinv_all)
52 stmdb sp!, {r4, r5, r6, r7, r8, r9}
55 ldr r0, .Lcoherency_level
59 /* For each cache level */
62 /* Get cache type for given level */
72 /* Get number of ways */
74 ands r4, r4, r1, lsr #3
79 ands r7, r7, r1, lsr #13
84 orr r6, r6, r9, lsl r5
85 orr r6, r6, r7, lsl r2
87 /* Clean and invalidate data cache by way/index */
99 ldmia sp!, {r4, r5, r6, r7, r8, r9}
101 END(armv7_dcache_wbinv_all)
103 ENTRY(armv7_idcache_wbinv_all)
105 bl armv7_dcache_wbinv_all
115 END(armv7_idcache_wbinv_all)
118 ENTRY(armv7_cpu_sleep)
119 dsb /* data synchronization barrier */
120 wfi /* wait for interrupt */
124 ENTRY(armv7_drain_writebuf)
127 END(armv7_drain_writebuf)