2 * Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
3 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
6 * Developed by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of MARVELL nor the names of contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <machine/asm.h>
34 __FBSDID("$FreeBSD$");
36 #include <machine/sysreg.h>
41 .word _C_LABEL(arm_cache_loc)
43 .word _C_LABEL(arm_cache_type)
44 .Larmv7_dcache_line_size:
45 .word _C_LABEL(arm_dcache_min_line_size)
46 .Larmv7_icache_line_size:
47 .word _C_LABEL(arm_icache_min_line_size)
48 .Larmv7_idcache_line_size:
49 .word _C_LABEL(arm_idcache_min_line_size)
57 #define PT_NOS (1 << 5)
60 #define PT_INNER_WT (1 << 0)
61 #define PT_INNER_WB ((1 << 0) | (1 << 6))
62 #define PT_INNER_WBWA (1 << 6)
64 #define PT_OUTER_WT (2 << 3)
65 #define PT_OUTER_WB (3 << 3)
66 #define PT_OUTER_WBWA (1 << 3)
69 #define PT_ATTR (PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS)
71 #define PT_ATTR (PT_INNER_WBWA|PT_OUTER_WBWA)
76 bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
93 ENTRY(armv7_tlb_flushID)
105 END(armv7_tlb_flushID)
107 ENTRY(armv7_tlb_flushID_SE)
111 mcr CP15_TLBIMVAAIS(r0)
120 END(armv7_tlb_flushID_SE)
122 /* Based on algorithm from ARM Architecture Reference Manual */
123 ENTRY(armv7_dcache_wbinv_all)
124 stmdb sp!, {r4, r5, r6, r7, r8, r9}
126 /* Get cache level */
127 ldr r0, .Lcoherency_level
131 /* For each cache level */
134 /* Get cache type for given level */
144 /* Get number of ways */
146 ands r4, r4, r1, lsr #3
151 ands r7, r7, r1, lsr #13
156 orr r6, r6, r9, lsl r5
157 orr r6, r6, r7, lsl r2
159 /* Clean and invalidate data cache by way/index */
171 ldmia sp!, {r4, r5, r6, r7, r8, r9}
173 END(armv7_dcache_wbinv_all)
175 ENTRY(armv7_idcache_wbinv_all)
177 bl armv7_dcache_wbinv_all
187 END(armv7_idcache_wbinv_all)
189 ENTRY(armv7_dcache_wb_range)
190 ldr ip, .Larmv7_dcache_line_size
201 dsb /* data synchronization barrier */
203 END(armv7_dcache_wb_range)
205 ENTRY(armv7_dcache_wbinv_range)
206 ldr ip, .Larmv7_dcache_line_size
213 mcr CP15_DCCIMVAC(r0)
216 bhi .Larmv7_wbinv_next
217 dsb /* data synchronization barrier */
219 END(armv7_dcache_wbinv_range)
222 * Note, we must not invalidate everything. If the range is too big we
223 * must use wb-inv of the entire cache.
225 ENTRY(armv7_dcache_inv_range)
226 ldr ip, .Larmv7_dcache_line_size
237 dsb /* data synchronization barrier */
239 END(armv7_dcache_inv_range)
241 ENTRY(armv7_idcache_wbinv_range)
242 ldr ip, .Larmv7_idcache_line_size
248 .Larmv7_id_wbinv_next:
250 mcr CP15_DCCIMVAC(r0)
253 bhi .Larmv7_id_wbinv_next
254 isb /* instruction synchronization barrier */
255 dsb /* data synchronization barrier */
257 END(armv7_idcache_wbinv_range)
259 ENTRY_NP(armv7_icache_sync_all)
265 isb /* instruction synchronization barrier */
266 dsb /* data synchronization barrier */
268 END(armv7_icache_sync_all)
270 ENTRY_NP(armv7_icache_sync_range)
271 ldr ip, .Larmv7_icache_line_size
278 bhi .Larmv7_sync_next
279 isb /* instruction synchronization barrier */
280 dsb /* data synchronization barrier */
282 END(armv7_icache_sync_range)
284 ENTRY(armv7_cpu_sleep)
285 dsb /* data synchronization barrier */
286 wfi /* wait for interrupt */
290 ENTRY(armv7_context_switch)
304 END(armv7_context_switch)
306 ENTRY(armv7_drain_writebuf)
309 END(armv7_drain_writebuf)
320 bic r3, r2, r0 /* Clear bits */
321 eor r3, r3, r1 /* XOR bits */
330 * Invalidate all I+D+branch cache. Used by startup code, which counts
331 * on the fact that only r0-r3,ip are modified and no stack space is used.
333 ENTRY(armv7_idcache_inv_all)
335 mcr CP15_CSSELR(r0) @ set cache level to L1
338 ubfx r2, r0, #13, #15 @ get num sets - 1 from CCSIDR
339 ubfx r3, r0, #3, #10 @ get numways - 1 from CCSIDR
340 clz r1, r3 @ number of bits to MSB of way
341 lsl r3, r3, r1 @ shift into position
343 lsl ip, ip, r1 @ ip now contains the way decr
345 ubfx r0, r0, #0, #3 @ get linesize from CCSIDR
346 add r0, r0, #4 @ apply bias
347 lsl r2, r2, r0 @ shift sets by log2(linesize)
348 add r3, r3, r2 @ merge numsets - 1 with numways - 1
349 sub ip, ip, r2 @ subtract numsets - 1 from way decr
351 lsl r1, r1, r0 @ r1 now contains the set decr
352 mov r2, ip @ r2 now contains set way decr
354 /* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
355 1: mcr CP15_DCISW(r3) @ invalidate line
356 movs r0, r3 @ get current way/set
357 beq 2f @ at 0 means we are done.
358 movs r0, r0, lsl #10 @ clear way bits leaving only set bits
359 subne r3, r3, r1 @ non-zero?, decrement set #
360 subeq r3, r3, r2 @ zero?, decrement way # and restore set count
363 2: dsb @ wait for stores to finish
365 mcr CP15_ICIALLU @ invalidate instruction+branch cache
366 isb @ instruction sync barrier
368 END(armv7_idcache_inv_all)
370 ENTRY_NP(armv7_sleep)