1 /* $NetBSD: cpufunc_asm_fa526.S,v 1.3 2008/10/15 16:56:49 matt Exp $*/
3 * Copyright (c) 2008 The NetBSD Foundation, Inc.
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas <matt@3am-software.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD$");
36 #define CACHELINE_SIZE 16
38 #define CACHELINE_SIZE 32
43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
50 /* If we have updated the TTB we must flush the TLB */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
53 /* Make sure that pipeline is emptied */
62 ENTRY(fa526_tlb_flushID_SE)
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
65 END(fa526_tlb_flushID_SE)
67 ENTRY(fa526_cpu_sleep)
71 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
78 ENTRY(fa526_idcache_wbinv_all)
80 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
81 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
82 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
84 END(fa526_idcache_wbinv_all)
86 ENTRY(fa526_dcache_wbinv_all)
88 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
89 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
91 END(fa526_dcache_wbinv_all)
96 ENTRY(fa526_dcache_wbinv_range)
98 bhs _C_LABEL(fa526_dcache_wbinv_all)
100 and r2, r0, #(CACHELINE_SIZE - 1)
102 bic r0, r0, #(CACHELINE_SIZE - 1)
104 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
105 add r0, r0, #CACHELINE_SIZE
106 subs r1, r1, #CACHELINE_SIZE
109 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
111 END(fa526_dcache_wbinv_range)
113 ENTRY(fa526_dcache_wb_range)
118 mcr p15, 0, r0, c7, c10, 0 /* clean entire D$ */
121 1: and r2, r0, #(CACHELINE_SIZE - 1)
123 bic r0, r0, #(CACHELINE_SIZE - 1)
125 2: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
126 add r0, r0, #CACHELINE_SIZE
127 subs r1, r1, #CACHELINE_SIZE
130 3: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
132 END(fa526_dcache_wb_range)
134 ENTRY(fa526_dcache_inv_range)
135 and r2, r0, #(CACHELINE_SIZE - 1)
137 bic r0, r0, #(CACHELINE_SIZE - 1)
139 1: mcr p15, 0, r0, c7, c6, 1 /* invalidate D$ single entry */
140 add r0, r0, #CACHELINE_SIZE
141 subs r1, r1, #CACHELINE_SIZE
145 END(fa526_dcache_inv_range)
147 ENTRY(fa526_idcache_wbinv_range)
149 bhs _C_LABEL(fa526_idcache_wbinv_all)
151 and r2, r0, #(CACHELINE_SIZE - 1)
153 bic r0, r0, #(CACHELINE_SIZE - 1)
155 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
156 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
157 add r0, r0, #CACHELINE_SIZE
158 subs r1, r1, #CACHELINE_SIZE
161 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
163 END(fa526_idcache_wbinv_range)
165 ENTRY(fa526_icache_sync_range)
167 bhs .Lfa526_icache_sync_all
169 and r2, r0, #(CACHELINE_SIZE - 1)
171 bic r0, r0, #(CACHELINE_SIZE - 1)
173 1: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
174 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
175 add r0, r0, #CACHELINE_SIZE
176 subs r1, r1, #CACHELINE_SIZE
179 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
182 .Lfa526_icache_sync_all:
184 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
186 END(fa526_icache_sync_range)
188 ENTRY(fa526_context_switch)
190 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
191 * Thus the data cache will contain only kernel data and the
192 * instruction cache will contain only kernel code, and all
193 * kernel mappings are shared by all processes.
196 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
198 /* If we have updated the TTB we must flush the TLB */
200 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
202 /* Make sure that pipeline is emptied */
206 END(fa526_context_switch)