2 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD$");
35 #include <machine/param.h>
37 .Lpj4b_cache_line_size:
38 .word _C_LABEL(arm_pdcache_line_size)
45 /* Cache synchronization is not required as this core has PIPT caches */
46 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
48 orr r0, r0, #2 /* Set TTB shared memory flag */
50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 ENTRY_NP(armv6_icache_sync_all)
57 * We assume that the code here can never be out of sync with the
58 * dcache, so that we can safely flush the Icache and fall through
59 * into the Dcache cleaning code.
62 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
63 mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */
64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
66 END(armv6_icache_sync_all)
68 ENTRY(pj4b_icache_sync_range)
71 mcrr p15, 0, r1, r0, c5 /* invalidate IC range */
72 mcrr p15, 0, r1, r0, c12 /* clean DC range */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
75 END(pj4b_icache_sync_range)
77 ENTRY(pj4b_dcache_inv_range)
78 ldr ip, .Lpj4b_cache_line_size
80 sub r1, r1, #1 /* Don't overrun */
86 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */
88 mcr p15, 0, r0, c7, c6, 1
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 END(pj4b_dcache_inv_range)
96 ENTRY(armv6_idcache_wbinv_all)
98 mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */
99 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
100 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
102 END(armv6_idcache_wbinv_all)
104 ENTRY(armv6_dcache_wbinv_all)
106 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
107 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
109 END(armv6_dcache_wbinv_all)
111 ENTRY(pj4b_idcache_wbinv_range)
112 ldr ip, .Lpj4b_cache_line_size
114 sub r1, r1, #1 /* Don't overrun */
120 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
123 /* Request for ownership */
127 mcr p15, 0, r0, c7, c5, 1
128 mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
132 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
134 END(pj4b_idcache_wbinv_range)
136 ENTRY(pj4b_dcache_wbinv_range)
137 ldr ip, .Lpj4b_cache_line_size
139 sub r1, r1, #1 /* Don't overrun */
145 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
148 /* Request for ownership */
152 mcr p15, 0, r0, c7, c14, 1
156 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
158 END(pj4b_dcache_wbinv_range)
160 ENTRY(pj4b_dcache_wb_range)
161 ldr ip, .Lpj4b_cache_line_size
163 sub r1, r1, #1 /* Don't overrun */
169 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
172 /* Request for ownership */
176 mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */
180 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
182 END(pj4b_dcache_wb_range)
184 ENTRY(pj4b_drain_readbuf)
185 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
187 END(pj4b_drain_readbuf)
189 ENTRY(pj4b_flush_brnchtgt_all)
190 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
192 END(pj4b_flush_brnchtgt_all)
194 ENTRY(pj4b_flush_brnchtgt_va)
195 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
197 END(pj4b_flush_brnchtgt_va)
200 mrc p15, 0, r0, c0, c0, 5
206 /* Set Auxiliary Debug Modes Control 0 register */
207 mrc p15, 1, r0, c15, c1, 0
208 /* ARMADAXP errata fix: ARM-CPU-6136 */
209 bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */
211 orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */
212 mcr p15, 1, r0, c15, c1, 0
214 /* Set Auxiliary Debug Modes Control 1 register */
215 mrc p15, 1, r0, c15, c1, 1
216 /* ARMADAXP errata fix: ARM-CPU-6409 */
217 bic r0, r0, #(1 << 2) /* Disable static branch prediction */
219 orr r0, r0, #(1 << 5) /* STREX backoff disable */
220 orr r0, r0, #(1 << 8) /* Internal parity handling disable */
221 orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */
222 mcr p15, 1, r0, c15, c1, 1
224 /* Set Auxiliary Function Modes Control 0 register */
225 mrc p15, 1, r0, c15, c2, 0
227 orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */
229 orr r0, r0, #(1 << 2) /* L1 parite enable */
230 orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */
231 mcr p15, 1, r0, c15, c2, 0
233 /* Set Auxiliary Debug Modes Control 2 register */
234 mrc p15, 1, r0, c15, c1, 2
235 bic r0, r0, #(1 << 23) /* Enable fast LDR */
236 orr r0, r0, #(1 << 25) /* Intervention Interleave disable */
237 orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */
238 orr r0, r0, #(1 << 29) /* Disable MO device read / write */
239 orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/
240 orr r0, r0, #(1 << 31) /* Enable write evict */
241 mcr p15, 1, r0, c15, c1, 2
243 /* Set SMP mode in Auxiliary Control Register */
244 mrc p15, 0, r0, c1, c0, 1
245 orr r0, r0, #(1 << 5)
246 mcr p15, 0, r0, c1, c0, 1
249 /* Load CPU number */
250 mrc p15, 0, r0, c0, c0, 5
253 /* SF Enable and invalidate */
254 ldr r1, .Lpj4b_sf_ctrl_reg
255 ldr r2, [r1, r0, lsl #8]
256 orr r2, r2, #(1 << 0)
257 bic r2, r2, #(1 << 8)
258 str r2, [r1, r0, lsl #8]