1 /* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */
4 * Copyright (c) 2007 Olivier Houchard
5 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
8 * Written by Allen Briggs and Jason R. Thorpe for Wasabi Systems, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
41 * Copyright (c) 2001 Matt Thomas.
42 * Copyright (c) 1997,1998 Mark Brinicombe.
43 * Copyright (c) 1997 Causality Limited
44 * All rights reserved.
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions
49 * 1. Redistributions of source code must retain the above copyright
50 * notice, this list of conditions and the following disclaimer.
51 * 2. Redistributions in binary form must reproduce the above copyright
52 * notice, this list of conditions and the following disclaimer in the
53 * documentation and/or other materials provided with the distribution.
54 * 3. All advertising materials mentioning features or use of this software
55 * must display the following acknowledgement:
56 * This product includes software developed by Causality Limited.
57 * 4. The name of Causality Limited may not be used to endorse or promote
58 * products derived from this software without specific prior written
61 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
62 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
63 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
64 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
65 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
66 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
73 * XScale core 3 assembly functions for CPU / MMU / TLB specific operations
76 #include <machine/armreg.h>
77 #include <machine/asm.h>
78 __FBSDID("$FreeBSD$");
81 * Size of the XScale core D-cache.
83 #define DCACHE_SIZE 0x00008000
86 * CPWAIT -- Canonical method to wait for CP15 update.
87 * From: Intel 80200 manual, section 2.3.3.
89 * NOTE: Clobbers the specified temp reg.
91 #define CPWAIT_BRANCH \
95 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
96 mov tmp, tmp /* wait for it to complete */ ;\
97 CPWAIT_BRANCH /* branch to next insn */
99 #define CPWAIT_AND_RETURN_SHIFTER lsr #32
101 #define CPWAIT_AND_RETURN(tmp) \
102 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
103 /* Wait for it to complete and branch to the return address */ \
104 sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER
106 #define ARM_USE_L2_CACHE
108 #define L2_CACHE_SIZE 0x80000
109 #define L2_CACHE_WAYS 8
110 #define L2_CACHE_LINE_SIZE 32
111 #define L2_CACHE_SETS (L2_CACHE_SIZE / \
112 (L2_CACHE_WAYS * L2_CACHE_LINE_SIZE))
114 #define L1_DCACHE_SIZE 32 * 1024
115 #define L1_DCACHE_WAYS 4
116 #define L1_DCACHE_LINE_SIZE 32
117 #define L1_DCACHE_SETS (L1_DCACHE_SIZE / \
118 (L1_DCACHE_WAYS * L1_DCACHE_LINE_SIZE))
119 #ifdef CACHE_CLEAN_BLOCK_INTR
120 #define XSCALE_CACHE_CLEAN_BLOCK \
123 orr r0, r4, #(PSR_I | PSR_F) ; \
126 #define XSCALE_CACHE_CLEAN_UNBLOCK \
127 msr cpsr_fsxc, r4 ; \
130 #define XSCALE_CACHE_CLEAN_BLOCK
131 #define XSCALE_CACHE_CLEAN_UNBLOCK
132 #endif /* CACHE_CLEAN_BLOCK_INTR */
135 ENTRY_NP(xscalec3_cache_syncI)
136 EENTRY_NP(xscalec3_cache_purgeID)
137 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
138 EENTRY_NP(xscalec3_cache_cleanID)
139 EENTRY_NP(xscalec3_cache_purgeD)
140 EENTRY(xscalec3_cache_cleanD)
142 XSCALE_CACHE_CLEAN_BLOCK
148 orr r3, r1, r2, asl #5
149 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */
151 cmp r2, #L1_DCACHE_SETS
157 XSCALE_CACHE_CLEAN_UNBLOCK
158 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
161 EEND(xscalec3_cache_purgeID)
162 EEND(xscalec3_cache_cleanID)
163 EEND(xscalec3_cache_purgeD)
164 EEND(xscalec3_cache_cleanD)
165 END(xscalec3_cache_syncI)
167 ENTRY(xscalec3_cache_purgeID_rng)
170 bcs _C_LABEL(xscalec3_cache_cleanID)
175 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */
177 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
184 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
186 CPWAIT_AND_RETURN(r0)
187 END(xscalec3_cache_purgeID_rng)
189 ENTRY(xscalec3_cache_syncI_rng)
191 bcs _C_LABEL(xscalec3_cache_syncI)
197 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
198 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
205 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
207 CPWAIT_AND_RETURN(r0)
208 END(xscalec3_cache_syncI_rng)
210 ENTRY(xscalec3_cache_purgeD_rng)
213 bcs _C_LABEL(xscalec3_cache_cleanID)
218 1: mcr p15, 0, r0, c7, c14, 1 /* Clean and invalidate D cache entry */
225 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
227 CPWAIT_AND_RETURN(r0)
228 END(xscalec3_cache_purgeD_rng)
230 ENTRY(xscalec3_cache_cleanID_rng)
231 EENTRY(xscalec3_cache_cleanD_rng)
234 bcs _C_LABEL(xscalec3_cache_cleanID)
239 1: mcr p15, 0, r0, c7, c10, 1 /* clean L1 D cache entry */
247 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
249 CPWAIT_AND_RETURN(r0)
250 EEND(xscalec3_cache_cleanD_rng)
251 END(xscalec3_cache_cleanID_rng)
253 ENTRY(xscalec3_l2cache_purge)
254 /* Clean-up the L2 cache */
255 mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
261 orr r3, r1, r2, asl #5
262 mcr p15, 1, r3, c7, c15, 2
264 cmp r2, #L2_CACHE_SETS
269 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
272 mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
274 END(xscalec3_l2cache_purge)
276 ENTRY(xscalec3_l2cache_clean_rng)
277 mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
283 1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */
291 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
292 mcr p15, 0, r0, c7, c10, 5
294 CPWAIT_AND_RETURN(r0)
295 END(xscalec3_l2cache_clean_rng)
297 ENTRY(xscalec3_l2cache_purge_rng)
299 mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
305 1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */
306 mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 D cache entry */
311 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
312 mcr p15, 0, r0, c7, c10, 5
314 CPWAIT_AND_RETURN(r0)
315 END(xscalec3_l2cache_purge_rng)
317 ENTRY(xscalec3_l2cache_flush_rng)
318 mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
324 1: mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 cache line */
328 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
329 mcr p15, 0, r0, c7, c10, 5
330 CPWAIT_AND_RETURN(r0)
331 END(xscalec3_l2cache_flush_rng)
334 * Functions to set the MMU Translation Table Base register
336 * We need to clean and flush the cache as it uses virtual
337 * addresses that are about to change.
339 ENTRY(xscalec3_setttb)
340 #ifdef CACHE_CLEAN_BLOCK_INTR
342 orr r1, r3, #(PSR_I | PSR_F)
345 stmfd sp!, {r0-r3, lr}
346 bl _C_LABEL(xscalec3_cache_cleanID)
347 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
348 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
352 ldmfd sp!, {r0-r3, lr}
354 #ifdef ARM_USE_L2_CACHE
355 orr r0, r0, #0x18 /* cache the page table in L2 */
358 mcr p15, 0, r0, c2, c0, 0
360 /* If we have updated the TTB we must flush the TLB */
361 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
365 #ifdef CACHE_CLEAN_BLOCK_INTR
376 * These is the CPU-specific parts of the context switcher cpu_switch()
377 * These functions actually perform the TTB reload.
379 * NOTE: Special calling convention
380 * r1, r4-r13 must be preserved
382 ENTRY(xscalec3_context_switch)
384 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
385 * Thus the data cache will contain only kernel data and the
386 * instruction cache will contain only kernel code, and all
387 * kernel mappings are shared by all processes.
389 #ifdef ARM_USE_L2_CACHE
390 orr r0, r0, #0x18 /* Cache the page table in L2 */
393 mcr p15, 0, r0, c2, c0, 0
395 /* If we have updated the TTB we must flush the TLB */
396 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
398 CPWAIT_AND_RETURN(r0)
399 END(xscalec3_context_switch)