2 * Copyright (c) 2015 Juniper Networks Inc.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/types.h>
40 #include <sys/systm.h>
42 #include <machine/atomic.h>
43 #include <machine/armreg.h>
44 #include <machine/cpu.h>
45 #include <machine/debug_monitor.h>
46 #include <machine/kdb.h>
47 #include <machine/pcb.h>
50 #include <ddb/db_access.h>
51 #include <ddb/db_sym.h>
54 DBG_TYPE_BREAKPOINT = 0,
55 DBG_TYPE_WATCHPOINT = 1,
60 enum dbg_access_t access;
66 static int dbg_reset_state(void);
67 static int dbg_setup_breakpoint(db_expr_t, db_expr_t, u_int);
68 static int dbg_remove_breakpoint(u_int);
69 static u_int dbg_find_slot(enum dbg_t, db_expr_t);
70 static boolean_t dbg_check_slot_free(enum dbg_t, u_int);
72 static int dbg_remove_xpoint(struct dbg_wb_conf *);
73 static int dbg_setup_xpoint(struct dbg_wb_conf *);
75 static int dbg_capable_var; /* Indicates that machine is capable of using
76 HW watchpoints/breakpoints */
78 static uint32_t dbg_model; /* Debug Arch. Model */
79 static boolean_t dbg_ossr; /* OS Save and Restore implemented */
81 static uint32_t dbg_watchpoint_num;
82 static uint32_t dbg_breakpoint_num;
84 /* ID_DFR0 - Debug Feature Register 0 */
85 #define ID_DFR0_CP_DEBUG_M_SHIFT 0
86 #define ID_DFR0_CP_DEBUG_M_MASK (0xF << ID_DFR0_CP_DEBUG_M_SHIFT)
87 #define ID_DFR0_CP_DEBUG_M_NS (0x0) /* Not supported */
88 #define ID_DFR0_CP_DEBUG_M_V6 (0x2) /* v6 Debug arch. CP14 access */
89 #define ID_DFR0_CP_DEBUG_M_V6_1 (0x3) /* v6.1 Debug arch. CP14 access */
90 #define ID_DFR0_CP_DEBUG_M_V7 (0x4) /* v7 Debug arch. CP14 access */
91 #define ID_DFR0_CP_DEBUG_M_V7_1 (0x5) /* v7.1 Debug arch. CP14 access */
93 /* DBGDIDR - Debug ID Register */
94 #define DBGDIDR_WRPS_SHIFT 28
95 #define DBGDIDR_WRPS_MASK (0xF << DBGDIDR_WRPS_SHIFT)
96 #define DBGDIDR_WRPS_NUM(reg) \
97 ((((reg) & DBGDIDR_WRPS_MASK) >> DBGDIDR_WRPS_SHIFT) + 1)
99 #define DBGDIDR_BRPS_SHIFT 24
100 #define DBGDIDR_BRPS_MASK (0xF << DBGDIDR_BRPS_SHIFT)
101 #define DBGDIDR_BRPS_NUM(reg) \
102 ((((reg) & DBGDIDR_BRPS_MASK) >> DBGDIDR_BRPS_SHIFT) + 1)
104 /* DBGPRSR - Device Powerdown and Reset Status Register */
105 #define DBGPRSR_PU (1 << 0) /* Powerup status */
107 /* DBGOSLSR - OS Lock Status Register */
108 #define DBGOSLSR_OSLM0 (1 << 0)
110 /* DBGOSDLR - OS Double Lock Register */
111 #define DBGPRSR_DLK (1 << 0) /* OS Double Lock set */
113 /* DBGDSCR - Debug Status and Control Register */
114 #define DBGSCR_MDBG_EN (1 << 15) /* Monitor debug-mode enable */
116 /* DBGWVR - Watchpoint Value Register */
117 #define DBGWVR_ADDR_MASK (~0x3U)
119 /* Watchpoints/breakpoints control register bitfields */
120 #define DBG_WB_CTRL_LEN_1 (0x1 << 5)
121 #define DBG_WB_CTRL_LEN_2 (0x3 << 5)
122 #define DBG_WB_CTRL_LEN_4 (0xf << 5)
123 #define DBG_WB_CTRL_LEN_8 (0xff << 5)
124 #define DBG_WB_CTRL_LEN_MASK(x) ((x) & (0xff << 5))
125 #define DBG_WB_CTRL_EXEC (0x0 << 3)
126 #define DBG_WB_CTRL_LOAD (0x1 << 3)
127 #define DBG_WB_CTRL_STORE (0x2 << 3)
128 #define DBG_WB_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3))
130 /* Common for breakpoint and watchpoint */
131 #define DBG_WB_CTRL_PL1 (0x1 << 1)
132 #define DBG_WB_CTRL_PL0 (0x2 << 1)
133 #define DBG_WB_CTRL_PLX_MASK(x) ((x) & (0x3 << 1))
134 #define DBG_WB_CTRL_E (0x1 << 0)
137 * Watchpoint/breakpoint helpers
139 #define DBG_BKPT_BT_SLOT 0 /* Slot for branch taken */
140 #define DBG_BKPT_BNT_SLOT 1 /* Slot for branch not taken */
144 /* Opc2 numbers for coprocessor instructions */
150 #define DBG_REG_BASE_BVR (DBG_WB_BVR << OP2_SHIFT)
151 #define DBG_REG_BASE_BCR (DBG_WB_BCR << OP2_SHIFT)
152 #define DBG_REG_BASE_WVR (DBG_WB_WVR << OP2_SHIFT)
153 #define DBG_REG_BASE_WCR (DBG_WB_WCR << OP2_SHIFT)
155 #define DBG_WB_READ(cn, cm, op2, val) do { \
156 __asm __volatile("mrc p14, 0, %0, " #cn "," #cm "," #op2 : "=r" (val)); \
159 #define DBG_WB_WRITE(cn, cm, op2, val) do { \
160 __asm __volatile("mcr p14, 0, %0, " #cn "," #cm "," #op2 :: "r" (val)); \
163 #define READ_WB_REG_CASE(op2, m, val) \
164 case (((op2) << OP2_SHIFT) + m): \
165 DBG_WB_READ(c0, c ## m, op2, val); \
168 #define WRITE_WB_REG_CASE(op2, m, val) \
169 case (((op2) << OP2_SHIFT) + m): \
170 DBG_WB_WRITE(c0, c ## m, op2, val); \
173 #define SWITCH_CASES_READ_WB_REG(op2, val) \
174 READ_WB_REG_CASE(op2, 0, val); \
175 READ_WB_REG_CASE(op2, 1, val); \
176 READ_WB_REG_CASE(op2, 2, val); \
177 READ_WB_REG_CASE(op2, 3, val); \
178 READ_WB_REG_CASE(op2, 4, val); \
179 READ_WB_REG_CASE(op2, 5, val); \
180 READ_WB_REG_CASE(op2, 6, val); \
181 READ_WB_REG_CASE(op2, 7, val); \
182 READ_WB_REG_CASE(op2, 8, val); \
183 READ_WB_REG_CASE(op2, 9, val); \
184 READ_WB_REG_CASE(op2, 10, val); \
185 READ_WB_REG_CASE(op2, 11, val); \
186 READ_WB_REG_CASE(op2, 12, val); \
187 READ_WB_REG_CASE(op2, 13, val); \
188 READ_WB_REG_CASE(op2, 14, val); \
189 READ_WB_REG_CASE(op2, 15, val)
191 #define SWITCH_CASES_WRITE_WB_REG(op2, val) \
192 WRITE_WB_REG_CASE(op2, 0, val); \
193 WRITE_WB_REG_CASE(op2, 1, val); \
194 WRITE_WB_REG_CASE(op2, 2, val); \
195 WRITE_WB_REG_CASE(op2, 3, val); \
196 WRITE_WB_REG_CASE(op2, 4, val); \
197 WRITE_WB_REG_CASE(op2, 5, val); \
198 WRITE_WB_REG_CASE(op2, 6, val); \
199 WRITE_WB_REG_CASE(op2, 7, val); \
200 WRITE_WB_REG_CASE(op2, 8, val); \
201 WRITE_WB_REG_CASE(op2, 9, val); \
202 WRITE_WB_REG_CASE(op2, 10, val); \
203 WRITE_WB_REG_CASE(op2, 11, val); \
204 WRITE_WB_REG_CASE(op2, 12, val); \
205 WRITE_WB_REG_CASE(op2, 13, val); \
206 WRITE_WB_REG_CASE(op2, 14, val); \
207 WRITE_WB_REG_CASE(op2, 15, val)
210 dbg_wb_read_reg(int reg, int n)
217 SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, val);
218 SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, val);
219 SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, val);
220 SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, val);
223 "trying to read from CP14 reg. using wrong opc2 %d\n",
231 dbg_wb_write_reg(int reg, int n, uint32_t val)
235 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, val);
236 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, val);
237 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, val);
238 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, val);
241 "trying to write to CP14 reg. using wrong opc2 %d\n",
247 static __inline boolean_t
251 return (atomic_cmpset_int(&dbg_capable_var, 0, 0) == 0);
255 kdb_cpu_pc_is_singlestep(db_addr_t pc)
258 * XXX: If the platform fails to enable its debug arch.
259 * there will be no stepping capabilities
264 if (dbg_find_slot(DBG_TYPE_BREAKPOINT, pc) != ~0U)
271 kdb_cpu_set_singlestep(void)
282 * Disable watchpoints, e.g. stepping over watched instruction will
283 * trigger break exception instead of single-step exception and locks
284 * CPU on that instruction for ever.
286 for (i = 0; i < dbg_watchpoint_num; i++) {
287 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
288 if ((wcr & DBG_WB_CTRL_E) != 0) {
289 dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
290 (wcr & ~DBG_WB_CTRL_E));
296 inst = db_get_value(pc, sizeof(pc), FALSE);
297 if (inst_branch(inst) || inst_call(inst) || inst_return(inst)) {
298 brpc = branch_taken(inst, pc);
299 dbg_setup_breakpoint(brpc, INSN_SIZE, DBG_BKPT_BT_SLOT);
301 pc = next_instr_address(pc, 0);
302 dbg_setup_breakpoint(pc, INSN_SIZE, DBG_BKPT_BNT_SLOT);
306 kdb_cpu_clear_singlestep(void)
314 dbg_remove_breakpoint(DBG_BKPT_BT_SLOT);
315 dbg_remove_breakpoint(DBG_BKPT_BNT_SLOT);
317 /* Restore all watchpoints */
318 for (i = 0; i < dbg_watchpoint_num; i++) {
319 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
320 wvr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);
321 /* Watchpoint considered not empty if address value is not 0 */
322 if ((wvr & DBGWVR_ADDR_MASK) != 0) {
323 dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
324 (wcr | DBG_WB_CTRL_E));
330 kdb_cpu_set_watchpoint(vm_offset_t addr, size_t size, int access)
332 enum dbg_access_t dbg_access;
335 case KDB_DBG_ACCESS_R:
336 dbg_access = HW_WATCHPOINT_R;
338 case KDB_DBG_ACCESS_W:
339 dbg_access = HW_WATCHPOINT_W;
341 case KDB_DBG_ACCESS_RW:
342 dbg_access = HW_WATCHPOINT_RW;
348 return (dbg_setup_watchpoint(addr, size, dbg_access));
352 kdb_cpu_clr_watchpoint(vm_offset_t addr, size_t size)
355 return (dbg_remove_watchpoint(addr, size));
359 dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_access_t access)
361 struct dbg_wb_conf conf;
363 if (access == HW_BREAKPOINT_X) {
364 db_printf("Invalid access type for watchpoint: %d\n", access);
370 conf.access = access;
371 conf.type = DBG_TYPE_WATCHPOINT;
373 return (dbg_setup_xpoint(&conf));
377 dbg_remove_watchpoint(db_expr_t addr, db_expr_t size __unused)
379 struct dbg_wb_conf conf;
382 conf.type = DBG_TYPE_WATCHPOINT;
384 return (dbg_remove_xpoint(&conf));
388 dbg_setup_breakpoint(db_expr_t addr, db_expr_t size, u_int slot)
390 struct dbg_wb_conf conf;
394 conf.access = HW_BREAKPOINT_X;
395 conf.type = DBG_TYPE_BREAKPOINT;
398 return (dbg_setup_xpoint(&conf));
402 dbg_remove_breakpoint(u_int slot)
404 struct dbg_wb_conf conf;
406 /* Slot already cleared. Don't recurse */
407 if (dbg_check_slot_free(DBG_TYPE_BREAKPOINT, slot))
411 conf.type = DBG_TYPE_BREAKPOINT;
413 return (dbg_remove_xpoint(&conf));
417 dbg_watchtype_str(uint32_t type)
421 case DBG_WB_CTRL_EXEC:
423 case DBG_WB_CTRL_STORE:
425 case DBG_WB_CTRL_LOAD:
427 case DBG_WB_CTRL_LOAD | DBG_WB_CTRL_STORE:
428 return ("read/write");
435 dbg_watchtype_len(uint32_t len)
439 case DBG_WB_CTRL_LEN_1:
441 case DBG_WB_CTRL_LEN_2:
443 case DBG_WB_CTRL_LEN_4:
445 case DBG_WB_CTRL_LEN_8:
453 dbg_show_watchpoint(void)
455 uint32_t wcr, len, type;
457 boolean_t is_enabled;
460 if (!dbg_capable()) {
461 db_printf("Architecture does not support HW "
462 "breakpoints/watchpoints\n");
466 db_printf("\nhardware watchpoints:\n");
467 db_printf(" watch status type len address symbol\n");
468 db_printf(" ----- -------- ---------- --- ---------- ------------------\n");
469 for (i = 0; i < dbg_watchpoint_num; i++) {
470 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
471 if ((wcr & DBG_WB_CTRL_E) != 0)
476 type = DBG_WB_CTRL_ACCESS_MASK(wcr);
477 len = DBG_WB_CTRL_LEN_MASK(wcr);
478 addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i) & DBGWVR_ADDR_MASK;
479 db_printf(" %-5d %-8s %10s %3d 0x%08x ", i,
480 is_enabled ? "enabled" : "disabled",
481 is_enabled ? dbg_watchtype_str(type) : "",
482 is_enabled ? dbg_watchtype_len(len) : 0,
484 db_printsym((db_addr_t)addr, DB_STGY_ANY);
490 dbg_check_slot_free(enum dbg_t type, u_int slot)
496 case DBG_TYPE_BREAKPOINT:
497 max = dbg_breakpoint_num;
498 cr = DBG_REG_BASE_BCR;
499 vr = DBG_REG_BASE_BVR;
501 case DBG_TYPE_WATCHPOINT:
502 max = dbg_watchpoint_num;
503 cr = DBG_REG_BASE_WCR;
504 vr = DBG_REG_BASE_WVR;
507 db_printf("%s: Unsupported event type %d\n", __func__, type);
512 db_printf("%s: Invalid slot number %d, max %d\n",
513 __func__, slot, max - 1);
517 if ((dbg_wb_read_reg(cr, slot) & DBG_WB_CTRL_E) == 0 &&
518 (dbg_wb_read_reg(vr, slot) & DBGWVR_ADDR_MASK) == 0)
525 dbg_find_free_slot(enum dbg_t type)
530 case DBG_TYPE_BREAKPOINT:
531 max = dbg_breakpoint_num;
533 case DBG_TYPE_WATCHPOINT:
534 max = dbg_watchpoint_num;
537 db_printf("Unsupported debug type\n");
541 for (i = 0; i < max; i++) {
542 if (dbg_check_slot_free(type, i))
550 dbg_find_slot(enum dbg_t type, db_expr_t addr)
552 uint32_t reg_addr, reg_ctrl;
556 case DBG_TYPE_BREAKPOINT:
557 max = dbg_breakpoint_num;
558 reg_addr = DBG_REG_BASE_BVR;
559 reg_ctrl = DBG_REG_BASE_BCR;
561 case DBG_TYPE_WATCHPOINT:
562 max = dbg_watchpoint_num;
563 reg_addr = DBG_REG_BASE_WVR;
564 reg_ctrl = DBG_REG_BASE_WCR;
567 db_printf("Unsupported debug type\n");
571 for (i = 0; i < max; i++) {
572 if ((dbg_wb_read_reg(reg_addr, i) == addr) &&
573 ((dbg_wb_read_reg(reg_ctrl, i) & DBG_WB_CTRL_E) != 0))
580 static __inline boolean_t
581 dbg_monitor_is_enabled(void)
584 return ((cp14_dbgdscrint_get() & DBGSCR_MDBG_EN) != 0);
588 dbg_enable_monitor(void)
592 /* Already enabled? Just return */
593 if (dbg_monitor_is_enabled())
596 dbg_dscr = cp14_dbgdscrint_get();
599 case ID_DFR0_CP_DEBUG_M_V6:
600 case ID_DFR0_CP_DEBUG_M_V6_1: /* fall through */
601 cp14_dbgdscr_v6_set(dbg_dscr | DBGSCR_MDBG_EN);
603 case ID_DFR0_CP_DEBUG_M_V7: /* fall through */
604 case ID_DFR0_CP_DEBUG_M_V7_1:
605 cp14_dbgdscr_v7_set(dbg_dscr | DBGSCR_MDBG_EN);
612 /* Verify that Monitor mode is set */
613 if (dbg_monitor_is_enabled())
620 dbg_setup_xpoint(struct dbg_wb_conf *conf)
625 uint32_t cr_size, cr_priv, cr_access;
626 uint32_t reg_ctrl, reg_addr, ctrl, addr;
634 is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
635 typestr = is_bkpt ? "breakpoint" : "watchpoint";
638 if (dbg_breakpoint_num == 0) {
639 db_printf("Breakpoints not supported on this architecture\n");
643 if (!dbg_check_slot_free(DBG_TYPE_BREAKPOINT, i)) {
645 * This should never happen. If it does it means that
646 * there is an erroneus scenario somewhere. Still, it can
647 * be done but let's inform the user.
649 db_printf("ERROR: Breakpoint already set. Replacing...\n");
652 i = dbg_find_free_slot(DBG_TYPE_WATCHPOINT);
654 db_printf("Can not find slot for %s, max %d slots supported\n",
655 typestr, dbg_watchpoint_num);
660 /* Kernel access only */
661 cr_priv = DBG_WB_CTRL_PL1;
665 cr_size = DBG_WB_CTRL_LEN_1;
668 cr_size = DBG_WB_CTRL_LEN_2;
671 cr_size = DBG_WB_CTRL_LEN_4;
674 cr_size = DBG_WB_CTRL_LEN_8;
677 db_printf("Unsupported address size for %s: %zu\n", typestr,
683 cr_access = DBG_WB_CTRL_EXEC;
684 reg_ctrl = DBG_REG_BASE_BCR;
685 reg_addr = DBG_REG_BASE_BVR;
686 /* Always unlinked BKPT */
687 ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);
689 switch(conf->access) {
690 case HW_WATCHPOINT_R:
691 cr_access = DBG_WB_CTRL_LOAD;
693 case HW_WATCHPOINT_W:
694 cr_access = DBG_WB_CTRL_STORE;
696 case HW_WATCHPOINT_RW:
697 cr_access = DBG_WB_CTRL_LOAD | DBG_WB_CTRL_STORE;
700 db_printf("Unsupported access type for %s: %d\n",
701 typestr, conf->access);
705 reg_ctrl = DBG_REG_BASE_WCR;
706 reg_addr = DBG_REG_BASE_WVR;
707 ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);
710 addr = conf->address;
712 dbg_wb_write_reg(reg_addr, i, addr);
713 dbg_wb_write_reg(reg_ctrl, i, ctrl);
716 * Save watchpoint settings for all CPUs.
717 * We don't need to do the same with breakpoints since HW breakpoints
718 * are only used to perform single stepping.
722 pcpu = pcpu_find(cpu);
723 /* Fill out the settings for watchpoint */
724 d = (struct dbreg *)pcpu->pc_dbreg;
725 d->dbg_wvr[i] = addr;
726 d->dbg_wcr[i] = ctrl;
727 /* Skip update command for the current CPU */
728 if (cpu != PCPU_GET(cpuid))
729 pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
732 /* Ensure all data is written before waking other CPUs */
733 atomic_thread_fence_rel();
739 dbg_remove_xpoint(struct dbg_wb_conf *conf)
743 uint32_t reg_ctrl, reg_addr, addr;
751 is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
752 addr = conf->address;
756 reg_ctrl = DBG_REG_BASE_BCR;
757 reg_addr = DBG_REG_BASE_BVR;
759 i = dbg_find_slot(DBG_TYPE_WATCHPOINT, addr);
761 db_printf("Can not find watchpoint for address 0%x\n", addr);
764 reg_ctrl = DBG_REG_BASE_WCR;
765 reg_addr = DBG_REG_BASE_WVR;
768 dbg_wb_write_reg(reg_ctrl, i, 0);
769 dbg_wb_write_reg(reg_addr, i, 0);
772 * Save watchpoint settings for all CPUs.
773 * We don't need to do the same with breakpoints since HW breakpoints
774 * are only used to perform single stepping.
778 pcpu = pcpu_find(cpu);
779 /* Fill out the settings for watchpoint */
780 d = (struct dbreg *)pcpu->pc_dbreg;
783 /* Skip update command for the current CPU */
784 if (cpu != PCPU_GET(cpuid))
785 pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
787 /* Ensure all data is written before waking other CPUs */
788 atomic_thread_fence_rel();
794 static __inline uint32_t
795 dbg_get_debug_model(void)
799 dbg_m = ((cpuinfo.id_dfr0 & ID_DFR0_CP_DEBUG_M_MASK) >>
800 ID_DFR0_CP_DEBUG_M_SHIFT);
805 static __inline boolean_t
810 case ID_DFR0_CP_DEBUG_M_V7:
811 if ((cp14_dbgoslsr_get() & DBGOSLSR_OSLM0) != 0)
815 case ID_DFR0_CP_DEBUG_M_V7_1:
822 static __inline boolean_t
823 dbg_arch_supported(void)
828 case ID_DFR0_CP_DEBUG_M_V6:
829 case ID_DFR0_CP_DEBUG_M_V6_1:
830 dbg_didr = cp14_dbgdidr_get();
832 * read-all-zeroes is used by QEMU
833 * to indicate that ARMv6 debug support
834 * is not implemented. Real hardware has at
835 * least version bits set
840 case ID_DFR0_CP_DEBUG_M_V7:
841 case ID_DFR0_CP_DEBUG_M_V7_1: /* fall through */
844 /* We only support valid v6.x/v7.x modes through CP14 */
849 static __inline uint32_t
850 dbg_get_wrp_num(void)
854 dbg_didr = cp14_dbgdidr_get();
856 return (DBGDIDR_WRPS_NUM(dbg_didr));
859 static __inline uint32_t
860 dgb_get_brp_num(void)
864 dbg_didr = cp14_dbgdidr_get();
866 return (DBGDIDR_BRPS_NUM(dbg_didr));
870 dbg_reset_state(void)
876 cpuid = PCPU_GET(cpuid);
880 case ID_DFR0_CP_DEBUG_M_V6:
881 case ID_DFR0_CP_DEBUG_M_V6_1: /* fall through */
883 * Arch needs monitor mode selected and enabled
884 * to be able to access breakpoint/watchpoint registers.
886 err = dbg_enable_monitor();
890 case ID_DFR0_CP_DEBUG_M_V7:
891 /* Is core power domain powered up? */
892 if ((cp14_dbgprsr_get() & DBGPRSR_PU) == 0)
901 case ID_DFR0_CP_DEBUG_M_V7_1:
902 /* Is double lock set? */
903 if ((cp14_dbgosdlr_get() & DBGPRSR_DLK) != 0)
912 db_printf("Debug facility locked (CPU%d)\n", cpuid);
917 * DBGOSLAR is always implemented for v7.1 Debug Arch. however is
918 * optional for v7 (depends on OS save and restore support).
920 if (((dbg_model & ID_DFR0_CP_DEBUG_M_V7_1) != 0) || dbg_ossr) {
923 * Writing any other value than 0xC5ACCESS will unlock.
925 cp14_dbgoslar_set(0);
931 * After reset we must ensure that DBGVCR has a defined value.
932 * Disable all vector catch events. Safe to use - required in all
939 * We have limited number of {watch,break}points, each consists of
941 * - wcr/bcr regsiter configurates corresponding {watch,break}point
943 * - wvr/bvr register keeps address we are hunting for
945 * Reset all breakpoints and watchpoints.
947 for (i = 0; i < dbg_watchpoint_num; ++i) {
948 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
949 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
952 for (i = 0; i < dbg_breakpoint_num; ++i) {
953 dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
954 dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
961 dbg_monitor_init(void)
963 #ifdef ARM_FORCE_DBG_MONITOR_DISABLE
964 db_printf("ARM Debug Architecture disabled in kernel compilation.\n");
969 /* Fetch ARM Debug Architecture model */
970 dbg_model = dbg_get_debug_model();
972 if (!dbg_arch_supported()) {
973 db_printf("ARM Debug Architecture not supported\n");
978 db_printf("ARM Debug Architecture %s\n",
979 (dbg_model == ID_DFR0_CP_DEBUG_M_V6) ? "v6" :
980 (dbg_model == ID_DFR0_CP_DEBUG_M_V6_1) ? "v6.1" :
981 (dbg_model == ID_DFR0_CP_DEBUG_M_V7) ? "v7" :
982 (dbg_model == ID_DFR0_CP_DEBUG_M_V7_1) ? "v7.1" : "unknown");
985 /* Do we have OS Save and Restore mechanism? */
986 dbg_ossr = dbg_get_ossr();
988 /* Find out many breakpoints and watchpoints we can use */
989 dbg_watchpoint_num = dbg_get_wrp_num();
990 dbg_breakpoint_num = dgb_get_brp_num();
993 db_printf("%d watchpoints and %d breakpoints supported\n",
994 dbg_watchpoint_num, dbg_breakpoint_num);
997 err = dbg_reset_state();
999 err = dbg_enable_monitor();
1001 atomic_set_int(&dbg_capable_var, 1);
1006 db_printf("HW Breakpoints/Watchpoints not enabled on CPU%d\n",
1008 #endif /* ARM_FORCE_DBG_MONITOR_DISABLE */
1011 CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg));
1014 dbg_monitor_init_secondary(void)
1018 * This flag is set on the primary CPU
1019 * and its meaning is valid for other CPUs too.
1024 err = dbg_reset_state();
1027 * Something is very wrong.
1028 * WPs/BPs will not work correctly on this CPU.
1030 KASSERT(0, ("%s: Failed to reset Debug Architecture "
1031 "state on CPU%d", __func__, PCPU_GET(cpuid)));
1032 /* Disable HW debug capabilities for all CPUs */
1033 atomic_set_int(&dbg_capable_var, 0);
1036 err = dbg_enable_monitor();
1038 KASSERT(0, ("%s: Failed to enable Debug Monitor"
1039 " on CPU%d", __func__, PCPU_GET(cpuid)));
1040 atomic_set_int(&dbg_capable_var, 0);
1045 dbg_resume_dbreg(void)
1051 * This flag is set on the primary CPU
1052 * and its meaning is valid for other CPUs too.
1057 atomic_thread_fence_acq();
1059 switch (PCPU_GET(dbreg_cmd)) {
1060 case PC_DBREG_CMD_LOAD:
1061 d = (struct dbreg *)PCPU_PTR(dbreg);
1063 /* Restore watchpoints */
1064 for (i = 0; i < dbg_watchpoint_num; i++) {
1065 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, d->dbg_wvr[i]);
1066 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, d->dbg_wcr[i]);
1069 PCPU_SET(dbreg_cmd, PC_DBREG_CMD_NONE);