2 * Copyright (c) 2015 Juniper Networks Inc.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/types.h>
39 #include <sys/systm.h>
41 #include <machine/atomic.h>
42 #include <machine/armreg.h>
43 #include <machine/cpu.h>
44 #include <machine/debug_monitor.h>
45 #include <machine/kdb.h>
46 #include <machine/pcb.h>
47 #include <machine/reg.h>
50 #include <ddb/db_access.h>
51 #include <ddb/db_sym.h>
54 DBG_TYPE_BREAKPOINT = 0,
55 DBG_TYPE_WATCHPOINT = 1,
60 enum dbg_access_t access;
66 static int dbg_reset_state(void);
67 static int dbg_setup_breakpoint(db_expr_t, db_expr_t, u_int);
68 static int dbg_remove_breakpoint(u_int);
69 static u_int dbg_find_slot(enum dbg_t, db_expr_t);
70 static boolean_t dbg_check_slot_free(enum dbg_t, u_int);
72 static int dbg_remove_xpoint(struct dbg_wb_conf *);
73 static int dbg_setup_xpoint(struct dbg_wb_conf *);
75 static int dbg_capable_var; /* Indicates that machine is capable of using
76 HW watchpoints/breakpoints */
78 static uint32_t dbg_model; /* Debug Arch. Model */
79 static boolean_t dbg_ossr; /* OS Save and Restore implemented */
81 static uint32_t dbg_watchpoint_num;
82 static uint32_t dbg_breakpoint_num;
84 /* ID_DFR0 - Debug Feature Register 0 */
85 #define ID_DFR0_CP_DEBUG_M_SHIFT 0
86 #define ID_DFR0_CP_DEBUG_M_MASK (0xF << ID_DFR0_CP_DEBUG_M_SHIFT)
87 #define ID_DFR0_CP_DEBUG_M_NS (0x0) /* Not supported */
88 #define ID_DFR0_CP_DEBUG_M_V6 (0x2) /* v6 Debug arch. CP14 access */
89 #define ID_DFR0_CP_DEBUG_M_V6_1 (0x3) /* v6.1 Debug arch. CP14 access */
90 #define ID_DFR0_CP_DEBUG_M_V7 (0x4) /* v7 Debug arch. CP14 access */
91 #define ID_DFR0_CP_DEBUG_M_V7_1 (0x5) /* v7.1 Debug arch. CP14 access */
93 /* DBGDIDR - Debug ID Register */
94 #define DBGDIDR_WRPS_SHIFT 28
95 #define DBGDIDR_WRPS_MASK (0xF << DBGDIDR_WRPS_SHIFT)
96 #define DBGDIDR_WRPS_NUM(reg) \
97 ((((reg) & DBGDIDR_WRPS_MASK) >> DBGDIDR_WRPS_SHIFT) + 1)
99 #define DBGDIDR_BRPS_SHIFT 24
100 #define DBGDIDR_BRPS_MASK (0xF << DBGDIDR_BRPS_SHIFT)
101 #define DBGDIDR_BRPS_NUM(reg) \
102 ((((reg) & DBGDIDR_BRPS_MASK) >> DBGDIDR_BRPS_SHIFT) + 1)
104 /* DBGPRSR - Device Powerdown and Reset Status Register */
105 #define DBGPRSR_PU (1 << 0) /* Powerup status */
107 /* DBGOSLSR - OS Lock Status Register */
108 #define DBGOSLSR_OSLM0 (1 << 0)
110 /* DBGOSDLR - OS Double Lock Register */
111 #define DBGPRSR_DLK (1 << 0) /* OS Double Lock set */
113 /* DBGDSCR - Debug Status and Control Register */
114 #define DBGSCR_MDBG_EN (1 << 15) /* Monitor debug-mode enable */
116 /* DBGWVR - Watchpoint Value Register */
117 #define DBGWVR_ADDR_MASK (~0x3U)
119 /* Watchpoints/breakpoints control register bitfields */
120 #define DBG_WB_CTRL_LEN_1 (0x1 << 5)
121 #define DBG_WB_CTRL_LEN_2 (0x3 << 5)
122 #define DBG_WB_CTRL_LEN_4 (0xf << 5)
123 #define DBG_WB_CTRL_LEN_8 (0xff << 5)
124 #define DBG_WB_CTRL_LEN_MASK(x) ((x) & (0xff << 5))
125 #define DBG_WB_CTRL_EXEC (0x0 << 3)
126 #define DBG_WB_CTRL_LOAD (0x1 << 3)
127 #define DBG_WB_CTRL_STORE (0x2 << 3)
128 #define DBG_WB_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3))
130 /* Common for breakpoint and watchpoint */
131 #define DBG_WB_CTRL_PL1 (0x1 << 1)
132 #define DBG_WB_CTRL_PL0 (0x2 << 1)
133 #define DBG_WB_CTRL_PLX_MASK(x) ((x) & (0x3 << 1))
134 #define DBG_WB_CTRL_E (0x1 << 0)
137 * Watchpoint/breakpoint helpers
139 #define DBG_BKPT_BT_SLOT 0 /* Slot for branch taken */
140 #define DBG_BKPT_BNT_SLOT 1 /* Slot for branch not taken */
144 /* Opc2 numbers for coprocessor instructions */
150 #define DBG_REG_BASE_BVR (DBG_WB_BVR << OP2_SHIFT)
151 #define DBG_REG_BASE_BCR (DBG_WB_BCR << OP2_SHIFT)
152 #define DBG_REG_BASE_WVR (DBG_WB_WVR << OP2_SHIFT)
153 #define DBG_REG_BASE_WCR (DBG_WB_WCR << OP2_SHIFT)
155 #define DBG_WB_READ(cn, cm, op2, val) do { \
156 __asm __volatile("mrc p14, 0, %0, " #cn "," #cm "," #op2 : "=r" (val)); \
159 #define DBG_WB_WRITE(cn, cm, op2, val) do { \
160 __asm __volatile("mcr p14, 0, %0, " #cn "," #cm "," #op2 :: "r" (val)); \
163 #define READ_WB_REG_CASE(op2, m, val) \
164 case (((op2) << OP2_SHIFT) + m): \
165 DBG_WB_READ(c0, c ## m, op2, val); \
168 #define WRITE_WB_REG_CASE(op2, m, val) \
169 case (((op2) << OP2_SHIFT) + m): \
170 DBG_WB_WRITE(c0, c ## m, op2, val); \
173 #define SWITCH_CASES_READ_WB_REG(op2, val) \
174 READ_WB_REG_CASE(op2, 0, val); \
175 READ_WB_REG_CASE(op2, 1, val); \
176 READ_WB_REG_CASE(op2, 2, val); \
177 READ_WB_REG_CASE(op2, 3, val); \
178 READ_WB_REG_CASE(op2, 4, val); \
179 READ_WB_REG_CASE(op2, 5, val); \
180 READ_WB_REG_CASE(op2, 6, val); \
181 READ_WB_REG_CASE(op2, 7, val); \
182 READ_WB_REG_CASE(op2, 8, val); \
183 READ_WB_REG_CASE(op2, 9, val); \
184 READ_WB_REG_CASE(op2, 10, val); \
185 READ_WB_REG_CASE(op2, 11, val); \
186 READ_WB_REG_CASE(op2, 12, val); \
187 READ_WB_REG_CASE(op2, 13, val); \
188 READ_WB_REG_CASE(op2, 14, val); \
189 READ_WB_REG_CASE(op2, 15, val)
191 #define SWITCH_CASES_WRITE_WB_REG(op2, val) \
192 WRITE_WB_REG_CASE(op2, 0, val); \
193 WRITE_WB_REG_CASE(op2, 1, val); \
194 WRITE_WB_REG_CASE(op2, 2, val); \
195 WRITE_WB_REG_CASE(op2, 3, val); \
196 WRITE_WB_REG_CASE(op2, 4, val); \
197 WRITE_WB_REG_CASE(op2, 5, val); \
198 WRITE_WB_REG_CASE(op2, 6, val); \
199 WRITE_WB_REG_CASE(op2, 7, val); \
200 WRITE_WB_REG_CASE(op2, 8, val); \
201 WRITE_WB_REG_CASE(op2, 9, val); \
202 WRITE_WB_REG_CASE(op2, 10, val); \
203 WRITE_WB_REG_CASE(op2, 11, val); \
204 WRITE_WB_REG_CASE(op2, 12, val); \
205 WRITE_WB_REG_CASE(op2, 13, val); \
206 WRITE_WB_REG_CASE(op2, 14, val); \
207 WRITE_WB_REG_CASE(op2, 15, val)
210 dbg_wb_read_reg(int reg, int n)
217 SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, val);
218 SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, val);
219 SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, val);
220 SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, val);
223 "trying to read from CP14 reg. using wrong opc2 %d\n",
231 dbg_wb_write_reg(int reg, int n, uint32_t val)
235 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, val);
236 SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, val);
237 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, val);
238 SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, val);
241 "trying to write to CP14 reg. using wrong opc2 %d\n",
247 static __inline boolean_t
251 return (atomic_cmpset_int(&dbg_capable_var, 0, 0) == 0);
255 kdb_cpu_pc_is_singlestep(db_addr_t pc)
258 * XXX: If the platform fails to enable its debug arch.
259 * there will be no stepping capabilities
260 * (SOFTWARE_SSTEP is not defined for __ARM_ARCH >= 6).
265 if (dbg_find_slot(DBG_TYPE_BREAKPOINT, pc) != ~0U)
272 kdb_cpu_set_singlestep(void)
283 * Disable watchpoints, e.g. stepping over watched instruction will
284 * trigger break exception instead of single-step exception and locks
285 * CPU on that instruction for ever.
287 for (i = 0; i < dbg_watchpoint_num; i++) {
288 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
289 if ((wcr & DBG_WB_CTRL_E) != 0) {
290 dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
291 (wcr & ~DBG_WB_CTRL_E));
297 inst = db_get_value(pc, sizeof(pc), FALSE);
298 if (inst_branch(inst) || inst_call(inst) || inst_return(inst)) {
299 brpc = branch_taken(inst, pc);
300 dbg_setup_breakpoint(brpc, INSN_SIZE, DBG_BKPT_BT_SLOT);
302 pc = next_instr_address(pc, 0);
303 dbg_setup_breakpoint(pc, INSN_SIZE, DBG_BKPT_BNT_SLOT);
307 kdb_cpu_clear_singlestep(void)
315 dbg_remove_breakpoint(DBG_BKPT_BT_SLOT);
316 dbg_remove_breakpoint(DBG_BKPT_BNT_SLOT);
318 /* Restore all watchpoints */
319 for (i = 0; i < dbg_watchpoint_num; i++) {
320 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
321 wvr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);
322 /* Watchpoint considered not empty if address value is not 0 */
323 if ((wvr & DBGWVR_ADDR_MASK) != 0) {
324 dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
325 (wcr | DBG_WB_CTRL_E));
331 dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_access_t access)
333 struct dbg_wb_conf conf;
335 if (access == HW_BREAKPOINT_X) {
336 db_printf("Invalid access type for watchpoint: %d\n", access);
342 conf.access = access;
343 conf.type = DBG_TYPE_WATCHPOINT;
345 return (dbg_setup_xpoint(&conf));
349 dbg_remove_watchpoint(db_expr_t addr, db_expr_t size __unused)
351 struct dbg_wb_conf conf;
354 conf.type = DBG_TYPE_WATCHPOINT;
356 return (dbg_remove_xpoint(&conf));
360 dbg_setup_breakpoint(db_expr_t addr, db_expr_t size, u_int slot)
362 struct dbg_wb_conf conf;
366 conf.access = HW_BREAKPOINT_X;
367 conf.type = DBG_TYPE_BREAKPOINT;
370 return (dbg_setup_xpoint(&conf));
374 dbg_remove_breakpoint(u_int slot)
376 struct dbg_wb_conf conf;
378 /* Slot already cleared. Don't recurse */
379 if (dbg_check_slot_free(DBG_TYPE_BREAKPOINT, slot))
383 conf.type = DBG_TYPE_BREAKPOINT;
385 return (dbg_remove_xpoint(&conf));
389 dbg_watchtype_str(uint32_t type)
393 case DBG_WB_CTRL_EXEC:
395 case DBG_WB_CTRL_STORE:
397 case DBG_WB_CTRL_LOAD:
399 case DBG_WB_CTRL_LOAD | DBG_WB_CTRL_STORE:
400 return ("read/write");
407 dbg_watchtype_len(uint32_t len)
411 case DBG_WB_CTRL_LEN_1:
413 case DBG_WB_CTRL_LEN_2:
415 case DBG_WB_CTRL_LEN_4:
417 case DBG_WB_CTRL_LEN_8:
425 dbg_show_watchpoint(void)
427 uint32_t wcr, len, type;
429 boolean_t is_enabled;
432 if (!dbg_capable()) {
433 db_printf("Architecture does not support HW "
434 "breakpoints/watchpoints\n");
438 db_printf("\nhardware watchpoints:\n");
439 db_printf(" watch status type len address symbol\n");
440 db_printf(" ----- -------- ---------- --- ---------- ------------------\n");
441 for (i = 0; i < dbg_watchpoint_num; i++) {
442 wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
443 if ((wcr & DBG_WB_CTRL_E) != 0)
448 type = DBG_WB_CTRL_ACCESS_MASK(wcr);
449 len = DBG_WB_CTRL_LEN_MASK(wcr);
450 addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i) & DBGWVR_ADDR_MASK;
451 db_printf(" %-5d %-8s %10s %3d 0x%08x ", i,
452 is_enabled ? "enabled" : "disabled",
453 is_enabled ? dbg_watchtype_str(type) : "",
454 is_enabled ? dbg_watchtype_len(len) : 0,
456 db_printsym((db_addr_t)addr, DB_STGY_ANY);
462 dbg_check_slot_free(enum dbg_t type, u_int slot)
468 case DBG_TYPE_BREAKPOINT:
469 max = dbg_breakpoint_num;
470 cr = DBG_REG_BASE_BCR;
471 vr = DBG_REG_BASE_BVR;
473 case DBG_TYPE_WATCHPOINT:
474 max = dbg_watchpoint_num;
475 cr = DBG_REG_BASE_WCR;
476 vr = DBG_REG_BASE_WVR;
479 db_printf("%s: Unsupported event type %d\n", __func__, type);
484 db_printf("%s: Invalid slot number %d, max %d\n",
485 __func__, slot, max - 1);
489 if ((dbg_wb_read_reg(cr, slot) & DBG_WB_CTRL_E) == 0 &&
490 (dbg_wb_read_reg(vr, slot) & DBGWVR_ADDR_MASK) == 0)
497 dbg_find_free_slot(enum dbg_t type)
502 case DBG_TYPE_BREAKPOINT:
503 max = dbg_breakpoint_num;
505 case DBG_TYPE_WATCHPOINT:
506 max = dbg_watchpoint_num;
509 db_printf("Unsupported debug type\n");
513 for (i = 0; i < max; i++) {
514 if (dbg_check_slot_free(type, i))
522 dbg_find_slot(enum dbg_t type, db_expr_t addr)
524 uint32_t reg_addr, reg_ctrl;
528 case DBG_TYPE_BREAKPOINT:
529 max = dbg_breakpoint_num;
530 reg_addr = DBG_REG_BASE_BVR;
531 reg_ctrl = DBG_REG_BASE_BCR;
533 case DBG_TYPE_WATCHPOINT:
534 max = dbg_watchpoint_num;
535 reg_addr = DBG_REG_BASE_WVR;
536 reg_ctrl = DBG_REG_BASE_WCR;
539 db_printf("Unsupported debug type\n");
543 for (i = 0; i < max; i++) {
544 if ((dbg_wb_read_reg(reg_addr, i) == addr) &&
545 ((dbg_wb_read_reg(reg_ctrl, i) & DBG_WB_CTRL_E) != 0))
552 static __inline boolean_t
553 dbg_monitor_is_enabled(void)
556 return ((cp14_dbgdscrint_get() & DBGSCR_MDBG_EN) != 0);
560 dbg_enable_monitor(void)
564 /* Already enabled? Just return */
565 if (dbg_monitor_is_enabled())
568 dbg_dscr = cp14_dbgdscrint_get();
571 case ID_DFR0_CP_DEBUG_M_V6:
572 case ID_DFR0_CP_DEBUG_M_V6_1: /* fall through */
573 cp14_dbgdscr_v6_set(dbg_dscr | DBGSCR_MDBG_EN);
575 case ID_DFR0_CP_DEBUG_M_V7: /* fall through */
576 case ID_DFR0_CP_DEBUG_M_V7_1:
577 cp14_dbgdscr_v7_set(dbg_dscr | DBGSCR_MDBG_EN);
584 /* Verify that Monitor mode is set */
585 if (dbg_monitor_is_enabled())
592 dbg_setup_xpoint(struct dbg_wb_conf *conf)
597 uint32_t cr_size, cr_priv, cr_access;
598 uint32_t reg_ctrl, reg_addr, ctrl, addr;
606 is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
607 typestr = is_bkpt ? "breakpoint" : "watchpoint";
610 if (dbg_breakpoint_num == 0) {
611 db_printf("Breakpoints not supported on this architecture\n");
615 if (!dbg_check_slot_free(DBG_TYPE_BREAKPOINT, i)) {
617 * This should never happen. If it does it means that
618 * there is an erroneus scenario somewhere. Still, it can
619 * be done but let's inform the user.
621 db_printf("ERROR: Breakpoint already set. Replacing...\n");
624 i = dbg_find_free_slot(DBG_TYPE_WATCHPOINT);
626 db_printf("Can not find slot for %s, max %d slots supported\n",
627 typestr, dbg_watchpoint_num);
632 /* Kernel access only */
633 cr_priv = DBG_WB_CTRL_PL1;
637 cr_size = DBG_WB_CTRL_LEN_1;
640 cr_size = DBG_WB_CTRL_LEN_2;
643 cr_size = DBG_WB_CTRL_LEN_4;
646 cr_size = DBG_WB_CTRL_LEN_8;
649 db_printf("Unsupported address size for %s\n", typestr);
654 cr_access = DBG_WB_CTRL_EXEC;
655 reg_ctrl = DBG_REG_BASE_BCR;
656 reg_addr = DBG_REG_BASE_BVR;
657 /* Always unlinked BKPT */
658 ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);
660 switch(conf->access) {
661 case HW_WATCHPOINT_R:
662 cr_access = DBG_WB_CTRL_LOAD;
664 case HW_WATCHPOINT_W:
665 cr_access = DBG_WB_CTRL_STORE;
667 case HW_WATCHPOINT_RW:
668 cr_access = DBG_WB_CTRL_LOAD | DBG_WB_CTRL_STORE;
671 db_printf("Unsupported exception level for %s\n", typestr);
675 reg_ctrl = DBG_REG_BASE_WCR;
676 reg_addr = DBG_REG_BASE_WVR;
677 ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);
680 addr = conf->address;
682 dbg_wb_write_reg(reg_addr, i, addr);
683 dbg_wb_write_reg(reg_ctrl, i, ctrl);
686 * Save watchpoint settings for all CPUs.
687 * We don't need to do the same with breakpoints since HW breakpoints
688 * are only used to perform single stepping.
692 pcpu = pcpu_find(cpu);
693 /* Fill out the settings for watchpoint */
694 d = (struct dbreg *)pcpu->pc_dbreg;
695 d->dbg_wvr[i] = addr;
696 d->dbg_wcr[i] = ctrl;
697 /* Skip update command for the current CPU */
698 if (cpu != PCPU_GET(cpuid))
699 pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
702 /* Ensure all data is written before waking other CPUs */
703 atomic_thread_fence_rel();
709 dbg_remove_xpoint(struct dbg_wb_conf *conf)
713 uint32_t reg_ctrl, reg_addr, addr;
721 is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
722 addr = conf->address;
726 reg_ctrl = DBG_REG_BASE_BCR;
727 reg_addr = DBG_REG_BASE_BVR;
729 i = dbg_find_slot(DBG_TYPE_WATCHPOINT, addr);
731 db_printf("Can not find watchpoint for address 0%x\n", addr);
734 reg_ctrl = DBG_REG_BASE_WCR;
735 reg_addr = DBG_REG_BASE_WVR;
738 dbg_wb_write_reg(reg_ctrl, i, 0);
739 dbg_wb_write_reg(reg_addr, i, 0);
742 * Save watchpoint settings for all CPUs.
743 * We don't need to do the same with breakpoints since HW breakpoints
744 * are only used to perform single stepping.
748 pcpu = pcpu_find(cpu);
749 /* Fill out the settings for watchpoint */
750 d = (struct dbreg *)pcpu->pc_dbreg;
753 /* Skip update command for the current CPU */
754 if (cpu != PCPU_GET(cpuid))
755 pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
757 /* Ensure all data is written before waking other CPUs */
758 atomic_thread_fence_rel();
764 static __inline uint32_t
765 dbg_get_debug_model(void)
769 dbg_m = ((cpuinfo.id_dfr0 & ID_DFR0_CP_DEBUG_M_MASK) >>
770 ID_DFR0_CP_DEBUG_M_SHIFT);
775 static __inline boolean_t
780 case ID_DFR0_CP_DEBUG_M_V7:
781 if ((cp14_dbgoslsr_get() & DBGOSLSR_OSLM0) != 0)
785 case ID_DFR0_CP_DEBUG_M_V7_1:
792 static __inline boolean_t
793 dbg_arch_supported(void)
797 case ID_DFR0_CP_DEBUG_M_V6:
798 case ID_DFR0_CP_DEBUG_M_V6_1:
799 case ID_DFR0_CP_DEBUG_M_V7:
800 case ID_DFR0_CP_DEBUG_M_V7_1: /* fall through */
803 /* We only support valid v6.x/v7.x modes through CP14 */
808 static __inline uint32_t
809 dbg_get_wrp_num(void)
813 dbg_didr = cp14_dbgdidr_get();
815 return (DBGDIDR_WRPS_NUM(dbg_didr));
818 static __inline uint32_t
819 dgb_get_brp_num(void)
823 dbg_didr = cp14_dbgdidr_get();
825 return (DBGDIDR_BRPS_NUM(dbg_didr));
829 dbg_reset_state(void)
835 cpuid = PCPU_GET(cpuid);
839 case ID_DFR0_CP_DEBUG_M_V6:
840 case ID_DFR0_CP_DEBUG_M_V6_1: /* fall through */
842 * Arch needs monitor mode selected and enabled
843 * to be able to access breakpoint/watchpoint registers.
845 err = dbg_enable_monitor();
849 case ID_DFR0_CP_DEBUG_M_V7:
850 /* Is core power domain powered up? */
851 if ((cp14_dbgprsr_get() & DBGPRSR_PU) == 0)
860 case ID_DFR0_CP_DEBUG_M_V7_1:
861 /* Is double lock set? */
862 if ((cp14_dbgosdlr_get() & DBGPRSR_DLK) != 0)
871 db_printf("Debug facility locked (CPU%d)\n", cpuid);
876 * DBGOSLAR is always implemented for v7.1 Debug Arch. however is
877 * optional for v7 (depends on OS save and restore support).
879 if (((dbg_model & ID_DFR0_CP_DEBUG_M_V7_1) != 0) || dbg_ossr) {
882 * Writing any other value than 0xC5ACCESS will unlock.
884 cp14_dbgoslar_set(0);
890 * After reset we must ensure that DBGVCR has a defined value.
891 * Disable all vector catch events. Safe to use - required in all
898 * We have limited number of {watch,break}points, each consists of
900 * - wcr/bcr regsiter configurates corresponding {watch,break}point
902 * - wvr/bvr register keeps address we are hunting for
904 * Reset all breakpoints and watchpoints.
906 for (i = 0; i < dbg_watchpoint_num; ++i) {
907 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
908 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
911 for (i = 0; i < dbg_breakpoint_num; ++i) {
912 dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
913 dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
920 dbg_monitor_init(void)
924 /* Fetch ARM Debug Architecture model */
925 dbg_model = dbg_get_debug_model();
927 if (!dbg_arch_supported()) {
928 db_printf("ARM Debug Architecture not supported\n");
933 db_printf("ARM Debug Architecture %s\n",
934 (dbg_model == ID_DFR0_CP_DEBUG_M_V6) ? "v6" :
935 (dbg_model == ID_DFR0_CP_DEBUG_M_V6_1) ? "v6.1" :
936 (dbg_model == ID_DFR0_CP_DEBUG_M_V7) ? "v7" :
937 (dbg_model == ID_DFR0_CP_DEBUG_M_V7_1) ? "v7.1" : "unknown");
940 /* Do we have OS Save and Restore mechanism? */
941 dbg_ossr = dbg_get_ossr();
943 /* Find out many breakpoints and watchpoints we can use */
944 dbg_watchpoint_num = dbg_get_wrp_num();
945 dbg_breakpoint_num = dgb_get_brp_num();
948 db_printf("%d watchpoints and %d breakpoints supported\n",
949 dbg_watchpoint_num, dbg_breakpoint_num);
952 err = dbg_reset_state();
954 err = dbg_enable_monitor();
956 atomic_set_int(&dbg_capable_var, 1);
961 db_printf("HW Breakpoints/Watchpoints not enabled on CPU%d\n",
965 CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg));
968 dbg_monitor_init_secondary(void)
973 * This flag is set on the primary CPU
974 * and its meaning is valid for other CPUs too.
979 cpuid = PCPU_GET(cpuid);
981 err = dbg_reset_state();
984 * Something is very wrong.
985 * WPs/BPs will not work correctly on this CPU.
987 KASSERT(0, ("%s: Failed to reset Debug Architecture "
988 "state on CPU%d", __func__, cpuid));
989 /* Disable HW debug capabilities for all CPUs */
990 atomic_set_int(&dbg_capable_var, 0);
993 err = dbg_enable_monitor();
995 KASSERT(0, ("%s: Failed to enable Debug Monitor"
996 " on CPU%d", __func__, cpuid));
997 atomic_set_int(&dbg_capable_var, 0);
1002 dbg_resume_dbreg(void)
1008 * This flag is set on the primary CPU
1009 * and its meaning is valid for other CPUs too.
1014 atomic_thread_fence_acq();
1016 switch (PCPU_GET(dbreg_cmd)) {
1017 case PC_DBREG_CMD_LOAD:
1018 d = (struct dbreg *)PCPU_PTR(dbreg);
1020 /* Restore watchpoints */
1021 for (i = 0; i < dbg_watchpoint_num; i++) {
1022 dbg_wb_write_reg(DBG_REG_BASE_WVR, i, d->dbg_wvr[i]);
1023 dbg_wb_write_reg(DBG_REG_BASE_WCR, i, d->dbg_wcr[i]);
1026 PCPU_SET(dbreg_cmd, PC_DBREG_CMD_NONE);