1 /* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */
4 * Copyright (c) 1996 Mark Brinicombe.
5 * Copyright (c) 1996 Brini.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of the company nor the name of the author may be used to
21 * endorse or promote products derived from this software without specific
22 * prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * RiscBSD kernel project
44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller &
47 * This code is not complete. Not all instructions are disassembled.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <machine/disassem.h>
57 #include <machine/armreg.h>
61 * General instruction format
63 * insn[cc][mod] [operands]
65 * Those fields with an uppercase format code indicate that the field
66 * follows directly after the instruction before the separator i.e.
67 * they modify the instruction rather than just being an operand to
68 * the instruction. The only exception is the writeback flag which
72 * 2 - print Operand 2 of a data processing instruction
73 * d - destination register (bits 12-15)
74 * n - n register (bits 16-19)
75 * s - s register (bits 8-11)
76 * o - indirect register rn (bits 16-19) (used by swap)
77 * m - m register (bits 0-3)
78 * a - address operand of ldr/str instruction
79 * l - register list for ldm/stm instruction
80 * f - 1st fp operand (register) (bits 12-14)
81 * g - 2nd fp operand (register) (bits 16-18)
82 * h - 3rd fp operand (register/immediate) (bits 0-4)
84 * t - thumb branch address (bits 24, 0-23)
85 * k - breakpoint comment (bits 0-3, 8-19)
86 * X - block transfer type
87 * Y - block transfer type (r13 base)
88 * c - comment field bits(0-23)
89 * p - saved or current status register
90 * F - PSR transfer fields
91 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
92 * L - co-processor transfer size
95 * Q - fp precision (for ldf/stf)
97 * v - co-processor data transfer registers + addressing mode
99 * x - instruction in hex
100 * # - co-processor number
101 * y - co-processor data processing registers
102 * z - co-processor register transfer registers
112 static const struct arm32_insn arm32_i[] = {
113 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
114 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
115 { 0x0f000000, 0x0f000000, "swi", "c" },
116 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
117 { 0x0f000000, 0x0a000000, "b", "b" },
118 { 0x0f000000, 0x0b000000, "bl", "b" },
119 { 0x0fe000f0, 0x00000090, "mul", "Snms" },
120 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" },
121 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" },
122 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" },
123 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" },
124 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" },
125 { 0x0d700000, 0x04200000, "strt", "daW" },
126 { 0x0d700000, 0x04300000, "ldrt", "daW" },
127 { 0x0d700000, 0x04600000, "strbt", "daW" },
128 { 0x0d700000, 0x04700000, "ldrbt", "daW" },
129 { 0x0c500000, 0x04000000, "str", "daW" },
130 { 0x0c500000, 0x04100000, "ldr", "daW" },
131 { 0x0c500000, 0x04400000, "strb", "daW" },
132 { 0x0c500000, 0x04500000, "ldrb", "daW" },
133 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */
134 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */
135 { 0x0e100000, 0x08000000, "stm", "XnWl" },
136 { 0x0e100000, 0x08100000, "ldm", "XnWl" },
137 { 0x0e1000f0, 0x00100090, "ldrb", "de" },
138 { 0x0e1000f0, 0x00000090, "strb", "de" },
139 { 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
140 { 0x0e1000f0, 0x001000b0, "ldrh", "de" },
141 { 0x0e1000f0, 0x000000b0, "strh", "de" },
142 { 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
143 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */
144 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */
145 { 0x0ff00ff0, 0x01000090, "swp", "dmo" },
146 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" },
147 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */
148 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */
149 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */
150 { 0x0ffffff0, 0x012fff10, "bx", "m" },
151 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" },
152 { 0x0ffffff0, 0x012fff30, "blx", "m" },
153 { 0xfff000f0, 0xe1200070, "bkpt", "k" },
154 { 0x0de00000, 0x00000000, "and", "Sdn2" },
155 { 0x0de00000, 0x00200000, "eor", "Sdn2" },
156 { 0x0de00000, 0x00400000, "sub", "Sdn2" },
157 { 0x0de00000, 0x00600000, "rsb", "Sdn2" },
158 { 0x0de00000, 0x00800000, "add", "Sdn2" },
159 { 0x0de00000, 0x00a00000, "adc", "Sdn2" },
160 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" },
161 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" },
162 { 0x0df00000, 0x01100000, "tst", "Dn2" },
163 { 0x0df00000, 0x01300000, "teq", "Dn2" },
164 { 0x0de00000, 0x01400000, "cmp", "Dn2" },
165 { 0x0de00000, 0x01600000, "cmn", "Dn2" },
166 { 0x0de00000, 0x01800000, "orr", "Sdn2" },
167 { 0x0de00000, 0x01a00000, "mov", "Sd2" },
168 { 0x0de00000, 0x01c00000, "bic", "Sdn2" },
169 { 0x0de00000, 0x01e00000, "mvn", "Sd2" },
170 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" },
171 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" },
172 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" },
173 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" },
174 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" },
175 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" },
176 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" },
177 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" },
178 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" },
179 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" },
180 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" },
181 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" },
182 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" },
183 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" },
184 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" },
185 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" },
186 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" },
187 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" },
188 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" },
189 { 0x0ff08f10, 0x0e508100, "log", "PRfh" },
190 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" },
191 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" },
192 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" },
193 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" },
194 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" },
195 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" },
196 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" },
197 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" },
198 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" },
199 { 0x0e100f00, 0x0c000100, "stf", "QLv" },
200 { 0x0e100f00, 0x0c100100, "ldf", "QLv" },
201 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" },
202 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" },
203 { 0x0ff00f10, 0x0e200110, "wfs", "d" },
204 { 0x0ff00f10, 0x0e300110, "rfs", "d" },
205 { 0x0ff00f10, 0x0e400110, "wfc", "d" },
206 { 0x0ff00f10, 0x0e500110, "rfc", "d" },
207 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" },
208 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" },
209 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" },
210 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" },
211 { 0xff100010, 0xfe000010, "mcr2", "#z" },
212 { 0x0f100010, 0x0e000010, "mcr", "#z" },
213 { 0xff100010, 0xfe100010, "mrc2", "#z" },
214 { 0x0f100010, 0x0e100010, "mrc", "#z" },
215 { 0xff000010, 0xfe000000, "cdp2", "#y" },
216 { 0x0f000010, 0x0e000000, "cdp", "#y" },
217 { 0xfe100090, 0xfc100000, "ldc2", "L#v" },
218 { 0x0e100090, 0x0c100000, "ldc", "L#v" },
219 { 0xfe100090, 0xfc000000, "stc2", "L#v" },
220 { 0x0e100090, 0x0c000000, "stc", "L#v" },
221 { 0x00000000, 0x00000000, NULL, NULL }
224 static char const arm32_insn_conditions[][4] = {
225 "eq", "ne", "cs", "cc",
226 "mi", "pl", "vs", "vc",
227 "hi", "ls", "ge", "lt",
231 static char const insn_block_transfers[][4] = {
232 "da", "ia", "db", "ib"
235 static char const insn_stack_block_transfers[][4] = {
236 "ed", "ea", "fd", "fa"
239 static char const op_shifts[][4] = {
240 "lsl", "lsr", "asr", "ror"
243 static char const insn_fpa_rounding[][2] = {
247 static char const insn_fpa_precision[][2] = {
251 static char const insn_fpaconstants[][8] = {
252 "0.0", "1.0", "2.0", "3.0",
253 "4.0", "5.0", "0.5", "10.0"
256 #define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f]
257 #define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3]
258 #define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3]
259 #define op2_shift(x) op_shifts[(x >> 5) & 3]
260 #define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03]
261 #define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]
262 #define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1]
263 #define insn_fpaimm(x) insn_fpaconstants[x & 0x07]
265 /* Local prototypes */
266 static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
267 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
268 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
270 static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
272 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
274 static u_int disassemble_readword(u_int address);
275 static void disassemble_printaddr(u_int address);
278 disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt)
280 struct arm32_insn *i_ptr = (struct arm32_insn *)&arm32_i;
290 insn = di->di_readword(loc);
292 /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
294 while (i_ptr->name) {
295 if ((insn & i_ptr->mask) == i_ptr->pattern) {
303 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn);
304 return(loc + INSN_SIZE);
307 /* If instruction forces condition code, don't print it. */
308 if ((i_ptr->mask & 0xf0000000) == 0xf0000000)
309 di->di_printf("%s", i_ptr->name);
311 di->di_printf("%s%s", i_ptr->name, insn_condition(insn));
313 f_ptr = i_ptr->format;
315 /* Insert tab if there are no instruction modifiers */
317 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') {
324 /* 2 - print Operand 2 of a data processing instruction */
326 if (insn & 0x02000000) {
327 int rotate= ((insn >> 7) & 0x1e);
329 di->di_printf("#0x%08x",
330 (insn & 0xff) << (32 - rotate) |
331 (insn & 0xff) >> rotate);
333 disasm_register_shift(di, insn);
336 /* d - destination register (bits 12-15) */
338 di->di_printf("r%d", ((insn >> 12) & 0x0f));
340 /* D - insert 'p' if Rd is R15 */
342 if (((insn >> 12) & 0x0f) == 15)
345 /* n - n register (bits 16-19) */
347 di->di_printf("r%d", ((insn >> 16) & 0x0f));
349 /* s - s register (bits 8-11) */
351 di->di_printf("r%d", ((insn >> 8) & 0x0f));
353 /* o - indirect register rn (bits 16-19) (used by swap) */
355 di->di_printf("[r%d]", ((insn >> 16) & 0x0f));
357 /* m - m register (bits 0-4) */
359 di->di_printf("r%d", ((insn >> 0) & 0x0f));
361 /* a - address operand of ldr/str instruction */
363 disasm_insn_ldrstr(di, insn, loc);
365 /* e - address operand of ldrh/strh instruction */
367 disasm_insn_ldrhstrh(di, insn, loc);
369 /* l - register list for ldm/stm instruction */
371 disasm_print_reglist(di, insn);
373 /* f - 1st fp operand (register) (bits 12-14) */
375 di->di_printf("f%d", (insn >> 12) & 7);
377 /* g - 2nd fp operand (register) (bits 16-18) */
379 di->di_printf("f%d", (insn >> 16) & 7);
381 /* h - 3rd fp operand (register/immediate) (bits 0-4) */
384 di->di_printf("#%s", insn_fpaimm(insn));
386 di->di_printf("f%d", insn & 7);
388 /* b - branch address */
390 branch = ((insn << 2) & 0x03ffffff);
391 if (branch & 0x02000000)
392 branch |= 0xfc000000;
393 di->di_printaddr(loc + 8 + branch);
395 /* t - blx address */
397 branch = ((insn << 2) & 0x03ffffff) |
398 (insn >> 23 & 0x00000002);
399 if (branch & 0x02000000)
400 branch |= 0xfc000000;
401 di->di_printaddr(loc + 8 + branch);
403 /* X - block transfer type */
405 di->di_printf("%s", insn_blktrans(insn));
407 /* Y - block transfer type (r13 base) */
409 di->di_printf("%s", insn_stkblktrans(insn));
411 /* c - comment field bits(0-23) */
413 di->di_printf("0x%08x", (insn & 0x00ffffff));
415 /* k - breakpoint comment (bits 0-3, 8-19) */
417 di->di_printf("0x%04x",
418 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f));
420 /* p - saved or current status register */
422 if (insn & 0x00400000)
423 di->di_printf("spsr");
425 di->di_printf("cpsr");
427 /* F - PSR transfer fields */
430 if (insn & (1 << 16))
432 if (insn & (1 << 17))
434 if (insn & (1 << 18))
436 if (insn & (1 << 19))
439 /* B - byte transfer flag */
441 if (insn & 0x00400000)
444 /* L - co-processor transfer size */
446 if (insn & (1 << 22))
449 /* S - set status flag */
451 if (insn & 0x00100000)
454 /* P - fp precision */
456 di->di_printf("%s", insn_fpaprec(insn));
458 /* Q - fp precision (for ldf/stf) */
461 /* R - fp rounding */
463 di->di_printf("%s", insn_fparnd(insn));
465 /* W - writeback flag */
467 if (insn & (1 << 21))
470 /* # - co-processor number */
472 di->di_printf("p%d", (insn >> 8) & 0x0f);
474 /* v - co-processor data transfer registers+addressing mode */
476 disasm_insn_ldcstc(di, insn, loc);
478 /* x - instruction in hex */
480 di->di_printf("0x%08x", insn);
482 /* y - co-processor data processing registers */
484 di->di_printf("%d, ", (insn >> 20) & 0x0f);
486 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f,
487 (insn >> 16) & 0x0f, insn & 0x0f);
489 di->di_printf(", %d", (insn >> 5) & 0x07);
491 /* z - co-processor register transfer registers */
493 di->di_printf("%d, ", (insn >> 21) & 0x07);
494 di->di_printf("r%d, c%d, c%d, %d",
495 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f,
496 insn & 0x0f, (insn >> 5) & 0x07);
498 /* if (((insn >> 5) & 0x07) != 0)
499 di->di_printf(", %d", (insn >> 5) & 0x07);*/
502 di->di_printf("[%c - unknown]", *f_ptr);
505 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z')
507 else if (*(++f_ptr)) {
518 return(loc + INSN_SIZE);
523 disasm_register_shift(const disasm_interface_t *di, u_int insn)
525 di->di_printf("r%d", (insn & 0x0f));
526 if ((insn & 0x00000ff0) == 0)
528 else if ((insn & 0x00000ff0) == 0x00000060)
529 di->di_printf(", rrx");
532 di->di_printf(", %s r%d", op2_shift(insn),
535 di->di_printf(", %s #%d", op2_shift(insn),
542 disasm_print_reglist(const disasm_interface_t *di, u_int insn)
552 for (loop = 0; loop < 17; ++loop) {
554 if (loop == 16 || !(insn & (1 << loop))) {
559 if (start == loop - 1)
560 di->di_printf("r%d", start);
562 di->di_printf("r%d-r%d", start, loop - 1);
566 if (insn & (1 << loop))
572 if (insn & (1 << 22))
577 disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
581 offset = insn & 0xfff;
582 if ((insn & 0x032f0000) == 0x010f0000) {
583 /* rA = pc, immediate index */
584 if (insn & 0x00800000)
588 di->di_printaddr(loc + 8);
590 di->di_printf("[r%d", (insn >> 16) & 0x0f);
591 if ((insn & 0x03000fff) != 0x01000000) {
592 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
593 if (!(insn & 0x00800000))
595 if (insn & (1 << 25))
596 disasm_register_shift(di, insn);
598 di->di_printf("#0x%03x", offset);
600 if (insn & (1 << 24))
606 disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
610 offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
611 if ((insn & 0x004f0000) == 0x004f0000) {
612 /* rA = pc, immediate index */
613 if (insn & 0x00800000)
617 di->di_printaddr(loc + 8);
619 di->di_printf("[r%d", (insn >> 16) & 0x0f);
620 if ((insn & 0x01400f0f) != 0x01400000) {
621 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
622 if (!(insn & 0x00800000))
624 if (insn & (1 << 22))
625 di->di_printf("#0x%02x", offset);
627 di->di_printf("r%d", (insn & 0x0f));
629 if (insn & (1 << 24))
635 disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
637 if (((insn >> 8) & 0xf) == 1)
638 di->di_printf("f%d, ", (insn >> 12) & 0x07);
640 di->di_printf("c%d, ", (insn >> 12) & 0x0f);
642 di->di_printf("[r%d", (insn >> 16) & 0x0f);
644 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
646 if (!(insn & (1 << 23)))
649 di->di_printf("#0x%03x", (insn & 0xff) << 2);
651 if (insn & (1 << 24))
654 if (insn & (1 << 21))
659 disassemble_readword(u_int address)
661 return(*((u_int *)address));
665 disassemble_printaddr(u_int address)
667 printf("0x%08x", address);
670 static const disasm_interface_t disassemble_di = {
671 disassemble_readword, disassemble_printaddr, db_printf
675 disassemble(u_int address)
678 (void)disasm(&disassemble_di, address, 0);
681 /* End of disassem.c */