2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Since we are compiled outside of the normal kernel build process, we
27 * need to include opt_global.h manually.
29 #include "opt_global.h"
30 #include "opt_kernname.h"
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 #include <machine/asm.h>
35 #include <sys/param.h>
36 #include <sys/elf32.h>
37 #include <sys/inflate.h>
38 #include <machine/elf.h>
39 #include <machine/pte.h>
40 #include <machine/cpufunc.h>
41 #include <machine/armreg.h>
43 extern char kernel_start[];
44 extern char kernel_end[];
52 extern unsigned int cpufunc_id(void);
53 extern void armv6_idcache_wbinv_all(void);
54 extern void armv7_idcache_wbinv_all(void);
55 extern void do_call(void *, void *, void *, int);
60 #define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
61 extern void arm9_idcache_wbinv_all(void);
62 #elif defined(CPU_FA526) || defined(CPU_FA626TE)
63 #define cpu_idcache_wbinv_all fa526_idcache_wbinv_all
64 extern void fa526_idcache_wbinv_all(void);
65 #elif defined(CPU_ARM9E)
66 #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
67 extern void armv5_ec_idcache_wbinv_all(void);
68 #elif defined(CPU_ARM10)
69 #define cpu_idcache_wbinv_all arm10_idcache_wbinv_all
70 extern void arm10_idcache_wbinv_all(void);
71 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
72 #define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
73 #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
74 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
75 defined(CPU_XSCALE_80219)
76 #define cpu_idcache_wbinv_all xscale_cache_purgeID
77 extern void xscale_cache_purgeID(void);
78 #elif defined(CPU_XSCALE_81342)
79 #define cpu_idcache_wbinv_all xscalec3_cache_purgeID
80 extern void xscalec3_cache_purgeID(void);
81 #elif defined(CPU_MV_PJ4B)
82 #if !defined(SOC_MV_ARMADAXP)
83 #define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
84 extern void armv6_idcache_wbinv_all(void);
86 #define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all
88 #endif /* CPU_MV_PJ4B */
89 #ifdef CPU_XSCALE_81342
90 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
91 extern void xscalec3_l2cache_purge(void);
92 #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
93 #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
94 extern void sheeva_l2cache_wbinv_all(void);
95 #elif defined(CPU_CORTEXA) || defined(CPU_KRAIT)
96 #define cpu_idcache_wbinv_all armv7_idcache_wbinv_all
97 #define cpu_l2cache_wbinv_all()
99 #define cpu_l2cache_wbinv_all()
102 static void armadaxp_idcache_wbinv_all(void);
104 int arm_picache_size;
105 int arm_picache_line_size;
106 int arm_picache_ways;
108 int arm_pdcache_size; /* and unified */
109 int arm_pdcache_line_size = 32;
110 int arm_pdcache_ways;
113 int arm_pcache_unified;
115 int arm_dcache_align;
116 int arm_dcache_align_mask;
118 u_int arm_cache_level;
119 u_int arm_cache_type[14];
122 /* Additional cache information local to this file. Log2 of some of the
124 static int arm_dcache_l2_nsets;
125 static int arm_dcache_l2_assoc;
126 static int arm_dcache_l2_linesize;
129 int block_userspace_access = 0;
130 extern int arm9_dcache_sets_inc;
131 extern int arm9_dcache_sets_max;
132 extern int arm9_dcache_index_max;
133 extern int arm9_dcache_index_inc;
135 static __inline void *
136 memcpy(void *dst, const void *src, int len)
142 if (0 && len >= 4 && !((vm_offset_t)d & 3) &&
143 !((vm_offset_t)s & 3)) {
144 *(uint32_t *)d = *(uint32_t *)s;
157 bzero(void *addr, int count)
159 char *tmp = (char *)addr;
162 if (count >= 4 && !((vm_offset_t)tmp & 3)) {
163 *(uint32_t *)tmp = 0;
174 static void arm9_setup(void);
180 unsigned int sp = ((unsigned int)&_end & ~3) + 4;
181 unsigned int pc, kernphysaddr;
184 * Figure out the physical address the kernel was loaded at. This
185 * assumes the entry point (this code right here) is in the first page,
186 * which will always be the case for this trampoline code.
188 __asm __volatile("mov %0, pc\n"
190 kernphysaddr = pc & ~PAGE_MASK;
192 #if defined(FLASHADDR) && defined(PHYSADDR) && defined(LOADERRAMADDR)
193 if ((FLASHADDR > LOADERRAMADDR && pc >= FLASHADDR) ||
194 (FLASHADDR < LOADERRAMADDR && pc < LOADERRAMADDR)) {
196 * We're running from flash, so just copy the whole thing
197 * from flash to memory.
198 * This is far from optimal, we could do the relocation or
199 * the unzipping directly from flash to memory to avoid this
200 * needless copy, but it would require to know the flash
203 unsigned int target_addr;
205 uint32_t src_addr = (uint32_t)&_start - PHYSADDR + FLASHADDR
206 + (pc - FLASHADDR - ((uint32_t)&_startC - PHYSADDR)) & 0xfffff000;
208 target_addr = (unsigned int)&_start - PHYSADDR + LOADERRAMADDR;
209 tmp_sp = target_addr + 0x100000 +
210 (unsigned int)&_end - (unsigned int)&_start;
211 memcpy((char *)target_addr, (char *)src_addr,
212 (unsigned int)&_end - (unsigned int)&_start);
213 /* Temporary set the sp and jump to the new location. */
217 : : "r" (target_addr), "r" (tmp_sp));
222 sp += KERNSIZE + 0x100;
223 sp &= ~(L1_TABLE_SIZE - 1);
224 sp += 2 * L1_TABLE_SIZE;
226 sp += 1024 * 1024; /* Should be enough for a stack */
228 __asm __volatile("adr %0, 2f\n"
229 "bic %0, %0, #0xff000000\n"
230 "and %1, %1, #0xff000000\n"
232 "mrc p15, 0, %1, c1, c0, 0\n"
233 "bic %1, %1, #1\n" /* Disable MMU */
234 "orr %1, %1, #(4 | 8)\n" /* Add DC enable,
236 "orr %1, %1, #0x1000\n" /* Add IC enable */
237 "orr %1, %1, #(0x800)\n" /* BPRD enable */
239 "mcr p15, 0, %1, c1, c0, 0\n"
246 : "=r" (tmp1), "+r" (kernphysaddr), "+r" (sp));
249 /* So that idcache_wbinv works; */
250 if ((cpufunc_id() & 0x0000f000) == 0x00009000)
260 u_int ctype, isize, dsize, cpuid;
261 u_int clevel, csize, i, sel;
265 __asm __volatile("mrc p15, 0, %0, c0, c0, 1"
268 cpuid = cpufunc_id();
270 * ...and thus spake the ARM ARM:
272 * If an <opcode2> value corresponding to an unimplemented or
273 * reserved ID register is encountered, the System Control
274 * processor returns the value of the main ID register.
279 if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
280 __asm __volatile("mrc p15, 1, %0, c0, c0, 1"
282 arm_cache_level = clevel;
283 arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level) + 1;
285 while ((type = (clevel & 0x7)) && i < 7) {
286 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
287 type == CACHE_SEP_CACHE) {
289 __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
291 __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
293 arm_cache_type[sel] = csize;
295 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
297 __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
299 __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
301 arm_cache_type[sel] = csize;
307 if ((ctype & CPU_CT_S) == 0)
308 arm_pcache_unified = 1;
311 * If you want to know how this code works, go read the ARM ARM.
314 arm_pcache_type = CPU_CT_CTYPE(ctype);
316 if (arm_pcache_unified == 0) {
317 isize = CPU_CT_ISIZE(ctype);
318 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
319 arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
320 if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
321 if (isize & CPU_CT_xSIZE_M)
322 arm_picache_line_size = 0; /* not present */
324 arm_picache_ways = 1;
326 arm_picache_ways = multiplier <<
327 (CPU_CT_xSIZE_ASSOC(isize) - 1);
329 arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
332 dsize = CPU_CT_DSIZE(ctype);
333 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
334 arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
335 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
336 if (dsize & CPU_CT_xSIZE_M)
337 arm_pdcache_line_size = 0; /* not present */
339 arm_pdcache_ways = 1;
341 arm_pdcache_ways = multiplier <<
342 (CPU_CT_xSIZE_ASSOC(dsize) - 1);
344 arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
346 arm_dcache_align = arm_pdcache_line_size;
348 arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2;
349 arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
350 arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
351 CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
354 arm_dcache_align_mask = arm_dcache_align - 1;
362 get_cachetype_cp15();
363 arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
364 arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
365 arm_dcache_l2_nsets)) - arm9_dcache_sets_inc;
366 arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
367 arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
371 armadaxp_idcache_wbinv_all(void)
375 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat));
376 if (feat & ARM_PFR0_THUMBEE_MASK)
377 armv7_idcache_wbinv_all();
379 armv6_idcache_wbinv_all();
383 static unsigned char *orig_input, *i_input, *i_output;
386 static u_int memcnt; /* Memory allocated: blocks */
387 static size_t memtot; /* Memory allocated: bytes */
389 * Library functions required by inflate().
392 #define MEMSIZ 0x8000
395 * Allocate memory block.
401 static u_char mem[MEMSIZ];
403 if (memtot + size > MEMSIZ)
412 * Free allocated memory block.
430 if ((size_t)(i_input - orig_input) >= KERNCOMPSIZE) {
437 output(void *dummy, unsigned char *ptr, unsigned long len)
441 memcpy(i_output, ptr, len);
447 inflate_kernel(void *kernel, void *startaddr)
450 unsigned char slide[GZ_WSIZE];
454 i_input = (unsigned char *)kernel + GZ_HEAD;
455 if (((char *)kernel)[3] & 0x18) {
460 i_output = startaddr;
461 bzero(&infl, sizeof(infl));
462 infl.gz_input = input;
463 infl.gz_output = output;
464 infl.gz_slide = slide;
466 return ((char *)(((vm_offset_t)i_output & ~3) + 4));
472 load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end,
476 Elf32_Phdr phdr[64] /* XXX */, *php;
477 Elf32_Shdr shdr[64] /* XXX */;
480 int symtabindex = -1;
481 int symstrindex = -1;
482 vm_offset_t lastaddr = 0;
486 eh = (Elf32_Ehdr *)kstart;
488 entry_point = (void*)eh->e_entry;
489 memcpy(phdr, (void *)(kstart + eh->e_phoff ),
490 eh->e_phnum * sizeof(phdr[0]));
492 /* Determine lastaddr. */
493 for (i = 0; i < eh->e_phnum; i++) {
494 if (lastaddr < (phdr[i].p_vaddr - KERNVIRTADDR + curaddr
496 lastaddr = phdr[i].p_vaddr - KERNVIRTADDR +
497 curaddr + phdr[i].p_memsz;
500 /* Save the symbol tables, as there're about to be scratched. */
501 memcpy(shdr, (void *)(kstart + eh->e_shoff),
502 sizeof(*shdr) * eh->e_shnum);
503 if (eh->e_shnum * eh->e_shentsize != 0 &&
505 for (i = 0; i < eh->e_shnum; i++) {
506 if (shdr[i].sh_type == SHT_SYMTAB) {
507 for (j = 0; j < eh->e_phnum; j++) {
508 if (phdr[j].p_type == PT_LOAD &&
515 shdr[i].sh_offset = 0;
520 if (shdr[i].sh_offset != 0 &&
521 shdr[i].sh_size != 0) {
523 symstrindex = shdr[i].sh_link;
527 func_end = roundup(func_end, sizeof(long));
528 if (symtabindex >= 0 && symstrindex >= 0) {
531 memcpy((void *)func_end, (void *)(
532 shdr[symtabindex].sh_offset + kstart),
533 shdr[symtabindex].sh_size);
534 memcpy((void *)(func_end +
535 shdr[symtabindex].sh_size),
536 (void *)(shdr[symstrindex].sh_offset +
537 kstart), shdr[symstrindex].sh_size);
539 lastaddr += shdr[symtabindex].sh_size;
540 lastaddr = roundup(lastaddr,
541 sizeof(shdr[symtabindex].sh_size));
542 lastaddr += sizeof(shdr[symstrindex].sh_size);
543 lastaddr += shdr[symstrindex].sh_size;
544 lastaddr = roundup(lastaddr,
545 sizeof(shdr[symstrindex].sh_size));
551 return ((void *)lastaddr);
554 for (i = 0; i < j; i++) {
557 if (phdr[i].p_type != PT_LOAD)
559 memcpy((void *)(phdr[i].p_vaddr - KERNVIRTADDR + curaddr),
560 (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz);
561 /* Clean space from oversized segments, eg: bss. */
562 if (phdr[i].p_filesz < phdr[i].p_memsz)
563 bzero((void *)(phdr[i].p_vaddr - KERNVIRTADDR +
564 curaddr + phdr[i].p_filesz), phdr[i].p_memsz -
567 /* Now grab the symbol tables. */
568 if (symtabindex >= 0 && symstrindex >= 0) {
569 *(Elf_Size *)lastaddr =
570 shdr[symtabindex].sh_size;
571 lastaddr += sizeof(shdr[symtabindex].sh_size);
572 memcpy((void*)lastaddr,
574 shdr[symtabindex].sh_size);
575 lastaddr += shdr[symtabindex].sh_size;
576 lastaddr = roundup(lastaddr,
577 sizeof(shdr[symtabindex].sh_size));
578 *(Elf_Size *)lastaddr =
579 shdr[symstrindex].sh_size;
580 lastaddr += sizeof(shdr[symstrindex].sh_size);
581 memcpy((void*)lastaddr,
583 shdr[symtabindex].sh_size),
584 shdr[symstrindex].sh_size);
585 lastaddr += shdr[symstrindex].sh_size;
586 lastaddr = roundup(lastaddr,
587 sizeof(shdr[symstrindex].sh_size));
588 *(Elf_Addr *)curaddr = MAGIC_TRAMP_NUMBER;
589 *((Elf_Addr *)curaddr + 1) = ssym - curaddr + KERNVIRTADDR;
590 *((Elf_Addr *)curaddr + 2) = lastaddr - curaddr + KERNVIRTADDR;
592 *(Elf_Addr *)curaddr = 0;
593 /* Invalidate the instruction cache. */
594 __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n"
595 "mcr p15, 0, %0, c7, c10, 4\n"
597 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
598 "bic %0, %0, #1\n" /* MMU_ENABLE */
599 "mcr p15, 0, %0, c1, c0, 0\n"
601 /* Jump to the entry point. */
602 ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))();
603 __asm __volatile(".globl func_end\n"
610 extern char func_end[];
613 #define PMAP_DOMAIN_KERNEL 0 /*
614 * Just define it instead of including the
615 * whole VM headers set.
619 setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend,
622 unsigned int *pd = (unsigned int *)pt_addr;
624 int domain = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT;
627 bzero(pd, L1_TABLE_SIZE);
628 for (addr = physstart; addr < physend; addr += L1_S_SIZE) {
629 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)|
630 L1_S_DOM(PMAP_DOMAIN_KERNEL) | addr;
632 pd[addr >> L1_S_SHIFT] |= L1_S_B;
635 if (0xfff00000 < physstart || 0xfff00000 > physend)
636 pd[0xfff00000 >> L1_S_SHIFT] = L1_TYPE_S|L1_S_AP(AP_KRW)|
637 L1_S_DOM(PMAP_DOMAIN_KERNEL)|physstart;
638 __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */
639 "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */
640 "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */
641 "mrc p15, 0, %0, c1, c0, 0\n"
642 "orr %0, %0, #1\n" /* MMU_ENABLE */
643 "mcr p15, 0, %0, c1, c0, 0\n"
644 "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */
647 "=r" (tmp) : "r" (pd), "r" (domain));
650 * XXX: This is the most stupid workaround I've ever wrote.
651 * For some reason, the KB9202 won't boot the kernel unless
652 * we access an address which is not in the
653 * 0x20000000 - 0x20ffffff range. I hope I'll understand
654 * what's going on later.
656 __hack = *(volatile int *)0xfffff21c;
664 char *kernel = (char *)&kernel_start;
668 __asm __volatile("mov %0, pc" :
670 curaddr = (void*)((unsigned int)curaddr & 0xfff00000);
672 if (*kernel == 0x1f && kernel[1] == 0x8b) {
673 pt_addr = (((int)&_end + KERNSIZE + 0x100) &
674 ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
677 /* So that idcache_wbinv works; */
678 if ((cpufunc_id() & 0x0000f000) == 0x00009000)
681 setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
682 (vm_paddr_t)curaddr + 0x10000000, 1);
684 dst = inflate_kernel(kernel, &_end);
685 kernel = (char *)&_end;
686 altdst = 4 + load_kernel((unsigned int)kernel,
687 (unsigned int)curaddr,
688 (unsigned int)&func_end + 800 , 0);
693 * Disable MMU. Otherwise, setup_pagetables call below
694 * might overwrite the L1 table we are currently using.
696 cpu_idcache_wbinv_all();
697 cpu_l2cache_wbinv_all();
698 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
699 "bic %0, %0, #1\n" /* MMU_DISABLE */
700 "mcr p15, 0, %0, c1, c0, 0\n"
704 dst = 4 + load_kernel((unsigned int)&kernel_start,
705 (unsigned int)curaddr,
706 (unsigned int)&func_end, 0);
707 dst = (void *)(((vm_offset_t)dst & ~3));
708 pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
709 setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
710 (vm_paddr_t)curaddr + 0x10000000, 0);
711 sp = pt_addr + L1_TABLE_SIZE + 8192;
713 dst = (void *)(sp + 4);
714 memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end -
715 (unsigned int)&load_kernel + 800);
716 do_call(dst, kernel, dst + (unsigned int)(&func_end) -
717 (unsigned int)(&load_kernel) + 800, sp);
721 /* We need to provide these functions but never call them */
722 void __aeabi_unwind_cpp_pr0(void);
723 void __aeabi_unwind_cpp_pr1(void);
724 void __aeabi_unwind_cpp_pr2(void);
726 __strong_reference(__aeabi_unwind_cpp_pr0, __aeabi_unwind_cpp_pr1);
727 __strong_reference(__aeabi_unwind_cpp_pr0, __aeabi_unwind_cpp_pr2);
729 __aeabi_unwind_cpp_pr0(void)