2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Since we are compiled outside of the normal kernel build process, we
27 * need to include opt_global.h manually.
29 #include "opt_global.h"
30 #include "opt_kernname.h"
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 #include <machine/asm.h>
35 #include <sys/param.h>
36 #include <sys/elf32.h>
37 #include <sys/inflate.h>
38 #include <machine/elf.h>
39 #include <machine/pte.h>
40 #include <machine/cpufunc.h>
41 #include <machine/armreg.h>
43 extern char kernel_start[];
44 extern char kernel_end[];
52 extern unsigned int cpufunc_id(void);
53 extern void armv6_idcache_wbinv_all(void);
54 extern void armv7_idcache_wbinv_all(void);
55 extern void do_call(void *, void *, void *, int);
60 #define cpu_idcache_wbinv_all arm7tdmi_cache_flushID
61 extern void arm7tdmi_cache_flushID(void);
62 #elif defined(CPU_ARM8)
63 #define cpu_idcache_wbinv_all arm8_cache_purgeID
64 extern void arm8_cache_purgeID(void);
65 #elif defined(CPU_ARM9)
66 #define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
67 extern void arm9_idcache_wbinv_all(void);
68 #elif defined(CPU_FA526) || defined(CPU_FA626TE)
69 #define cpu_idcache_wbinv_all fa526_idcache_wbinv_all
70 extern void fa526_idcache_wbinv_all(void);
71 #elif defined(CPU_ARM9E)
72 #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
73 extern void armv5_ec_idcache_wbinv_all(void);
74 #elif defined(CPU_ARM10)
75 #define cpu_idcache_wbinv_all arm10_idcache_wbinv_all
76 extern void arm10_idcache_wbinv_all(void);
77 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
78 #define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
79 #elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \
81 #define cpu_idcache_wbinv_all sa1_cache_purgeID
82 extern void sa1_cache_purgeID(void);
83 #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
84 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
85 defined(CPU_XSCALE_80219)
86 #define cpu_idcache_wbinv_all xscale_cache_purgeID
87 extern void xscale_cache_purgeID(void);
88 #elif defined(CPU_XSCALE_81342)
89 #define cpu_idcache_wbinv_all xscalec3_cache_purgeID
90 extern void xscalec3_cache_purgeID(void);
91 #elif defined(CPU_MV_PJ4B)
92 #if !defined(SOC_MV_ARMADAXP)
93 #define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
94 extern void armv6_idcache_wbinv_all(void);
96 #define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all
98 #endif /* CPU_MV_PJ4B */
99 #ifdef CPU_XSCALE_81342
100 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
101 extern void xscalec3_l2cache_purge(void);
102 #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
103 #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
104 extern void sheeva_l2cache_wbinv_all(void);
105 #elif defined(CPU_CORTEXA)
106 #define cpu_idcache_wbinv_all armv7_idcache_wbinv_all
107 #define cpu_l2cache_wbinv_all()
109 #define cpu_l2cache_wbinv_all()
112 static void armadaxp_idcache_wbinv_all(void);
114 int arm_picache_size;
115 int arm_picache_line_size;
116 int arm_picache_ways;
118 int arm_pdcache_size; /* and unified */
119 int arm_pdcache_line_size = 32;
120 int arm_pdcache_ways;
123 int arm_pcache_unified;
125 int arm_dcache_align;
126 int arm_dcache_align_mask;
128 u_int arm_cache_level;
129 u_int arm_cache_type[14];
132 /* Additional cache information local to this file. Log2 of some of the
134 static int arm_dcache_l2_nsets;
135 static int arm_dcache_l2_assoc;
136 static int arm_dcache_l2_linesize;
139 int block_userspace_access = 0;
140 extern int arm9_dcache_sets_inc;
141 extern int arm9_dcache_sets_max;
142 extern int arm9_dcache_index_max;
143 extern int arm9_dcache_index_inc;
145 static __inline void *
146 memcpy(void *dst, const void *src, int len)
152 if (0 && len >= 4 && !((vm_offset_t)d & 3) &&
153 !((vm_offset_t)s & 3)) {
154 *(uint32_t *)d = *(uint32_t *)s;
167 bzero(void *addr, int count)
169 char *tmp = (char *)addr;
172 if (count >= 4 && !((vm_offset_t)tmp & 3)) {
173 *(uint32_t *)tmp = 0;
184 static void arm9_setup(void);
189 int physaddr = KERNPHYSADDR;
191 unsigned int sp = ((unsigned int)&_end & ~3) + 4;
192 #if defined(FLASHADDR) && defined(LOADERRAMADDR)
195 __asm __volatile("mov %0, pc\n"
197 if ((FLASHADDR > LOADERRAMADDR && pc >= FLASHADDR) ||
198 (FLASHADDR < LOADERRAMADDR && pc < LOADERRAMADDR)) {
200 * We're running from flash, so just copy the whole thing
201 * from flash to memory.
202 * This is far from optimal, we could do the relocation or
203 * the unzipping directly from flash to memory to avoid this
204 * needless copy, but it would require to know the flash
207 unsigned int target_addr;
209 uint32_t src_addr = (uint32_t)&_start - PHYSADDR + FLASHADDR
210 + (pc - FLASHADDR - ((uint32_t)&_startC - PHYSADDR)) & 0xfffff000;
212 target_addr = (unsigned int)&_start - PHYSADDR + LOADERRAMADDR;
213 tmp_sp = target_addr + 0x100000 +
214 (unsigned int)&_end - (unsigned int)&_start;
215 memcpy((char *)target_addr, (char *)src_addr,
216 (unsigned int)&_end - (unsigned int)&_start);
217 /* Temporary set the sp and jump to the new location. */
221 : : "r" (target_addr), "r" (tmp_sp));
226 sp += KERNSIZE + 0x100;
227 sp &= ~(L1_TABLE_SIZE - 1);
228 sp += 2 * L1_TABLE_SIZE;
230 sp += 1024 * 1024; /* Should be enough for a stack */
232 __asm __volatile("adr %0, 2f\n"
233 "bic %0, %0, #0xff000000\n"
234 "and %1, %1, #0xff000000\n"
236 "mrc p15, 0, %1, c1, c0, 0\n"
237 "bic %1, %1, #1\n" /* Disable MMU */
238 "orr %1, %1, #(4 | 8)\n" /* Add DC enable,
240 "orr %1, %1, #0x1000\n" /* Add IC enable */
241 "orr %1, %1, #(0x800)\n" /* BPRD enable */
243 "mcr p15, 0, %1, c1, c0, 0\n"
250 : "=r" (tmp1), "+r" (physaddr), "+r" (sp));
253 /* So that idcache_wbinv works; */
254 if ((cpufunc_id() & 0x0000f000) == 0x00009000)
264 u_int ctype, isize, dsize, cpuid;
265 u_int clevel, csize, i, sel;
269 __asm __volatile("mrc p15, 0, %0, c0, c0, 1"
272 cpuid = cpufunc_id();
274 * ...and thus spake the ARM ARM:
276 * If an <opcode2> value corresponding to an unimplemented or
277 * reserved ID register is encountered, the System Control
278 * processor returns the value of the main ID register.
283 if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
284 __asm __volatile("mrc p15, 1, %0, c0, c0, 1"
286 arm_cache_level = clevel;
287 arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level) + 1;
289 while ((type = (clevel & 0x7)) && i < 7) {
290 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
291 type == CACHE_SEP_CACHE) {
293 __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
295 __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
297 arm_cache_type[sel] = csize;
299 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
301 __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
303 __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
305 arm_cache_type[sel] = csize;
311 if ((ctype & CPU_CT_S) == 0)
312 arm_pcache_unified = 1;
315 * If you want to know how this code works, go read the ARM ARM.
318 arm_pcache_type = CPU_CT_CTYPE(ctype);
320 if (arm_pcache_unified == 0) {
321 isize = CPU_CT_ISIZE(ctype);
322 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
323 arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
324 if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
325 if (isize & CPU_CT_xSIZE_M)
326 arm_picache_line_size = 0; /* not present */
328 arm_picache_ways = 1;
330 arm_picache_ways = multiplier <<
331 (CPU_CT_xSIZE_ASSOC(isize) - 1);
333 arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
336 dsize = CPU_CT_DSIZE(ctype);
337 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
338 arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
339 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
340 if (dsize & CPU_CT_xSIZE_M)
341 arm_pdcache_line_size = 0; /* not present */
343 arm_pdcache_ways = 1;
345 arm_pdcache_ways = multiplier <<
346 (CPU_CT_xSIZE_ASSOC(dsize) - 1);
348 arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
350 arm_dcache_align = arm_pdcache_line_size;
352 arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2;
353 arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
354 arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
355 CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
358 arm_dcache_align_mask = arm_dcache_align - 1;
366 get_cachetype_cp15();
367 arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
368 arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
369 arm_dcache_l2_nsets)) - arm9_dcache_sets_inc;
370 arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
371 arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
375 armadaxp_idcache_wbinv_all(void)
379 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat));
380 if (feat & ARM_PFR0_THUMBEE_MASK)
381 armv7_idcache_wbinv_all();
383 armv6_idcache_wbinv_all();
387 static unsigned char *orig_input, *i_input, *i_output;
390 static u_int memcnt; /* Memory allocated: blocks */
391 static size_t memtot; /* Memory allocated: bytes */
393 * Library functions required by inflate().
396 #define MEMSIZ 0x8000
399 * Allocate memory block.
405 static u_char mem[MEMSIZ];
407 if (memtot + size > MEMSIZ)
416 * Free allocated memory block.
434 if ((size_t)(i_input - orig_input) >= KERNCOMPSIZE) {
441 output(void *dummy, unsigned char *ptr, unsigned long len)
445 memcpy(i_output, ptr, len);
451 inflate_kernel(void *kernel, void *startaddr)
454 unsigned char slide[GZ_WSIZE];
458 i_input = (unsigned char *)kernel + GZ_HEAD;
459 if (((char *)kernel)[3] & 0x18) {
464 i_output = startaddr;
465 bzero(&infl, sizeof(infl));
466 infl.gz_input = input;
467 infl.gz_output = output;
468 infl.gz_slide = slide;
470 return ((char *)(((vm_offset_t)i_output & ~3) + 4));
476 load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end,
480 Elf32_Phdr phdr[64] /* XXX */, *php;
481 Elf32_Shdr shdr[64] /* XXX */;
484 int symtabindex = -1;
485 int symstrindex = -1;
486 vm_offset_t lastaddr = 0;
490 eh = (Elf32_Ehdr *)kstart;
492 entry_point = (void*)eh->e_entry;
493 memcpy(phdr, (void *)(kstart + eh->e_phoff ),
494 eh->e_phnum * sizeof(phdr[0]));
496 /* Determine lastaddr. */
497 for (i = 0; i < eh->e_phnum; i++) {
498 if (lastaddr < (phdr[i].p_vaddr - KERNVIRTADDR + curaddr
500 lastaddr = phdr[i].p_vaddr - KERNVIRTADDR +
501 curaddr + phdr[i].p_memsz;
504 /* Save the symbol tables, as there're about to be scratched. */
505 memcpy(shdr, (void *)(kstart + eh->e_shoff),
506 sizeof(*shdr) * eh->e_shnum);
507 if (eh->e_shnum * eh->e_shentsize != 0 &&
509 for (i = 0; i < eh->e_shnum; i++) {
510 if (shdr[i].sh_type == SHT_SYMTAB) {
511 for (j = 0; j < eh->e_phnum; j++) {
512 if (phdr[j].p_type == PT_LOAD &&
519 shdr[i].sh_offset = 0;
524 if (shdr[i].sh_offset != 0 &&
525 shdr[i].sh_size != 0) {
527 symstrindex = shdr[i].sh_link;
531 func_end = roundup(func_end, sizeof(long));
532 if (symtabindex >= 0 && symstrindex >= 0) {
535 memcpy((void *)func_end, (void *)(
536 shdr[symtabindex].sh_offset + kstart),
537 shdr[symtabindex].sh_size);
538 memcpy((void *)(func_end +
539 shdr[symtabindex].sh_size),
540 (void *)(shdr[symstrindex].sh_offset +
541 kstart), shdr[symstrindex].sh_size);
543 lastaddr += shdr[symtabindex].sh_size;
544 lastaddr = roundup(lastaddr,
545 sizeof(shdr[symtabindex].sh_size));
546 lastaddr += sizeof(shdr[symstrindex].sh_size);
547 lastaddr += shdr[symstrindex].sh_size;
548 lastaddr = roundup(lastaddr,
549 sizeof(shdr[symstrindex].sh_size));
555 return ((void *)lastaddr);
558 for (i = 0; i < j; i++) {
561 if (phdr[i].p_type != PT_LOAD)
563 memcpy((void *)(phdr[i].p_vaddr - KERNVIRTADDR + curaddr),
564 (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz);
565 /* Clean space from oversized segments, eg: bss. */
566 if (phdr[i].p_filesz < phdr[i].p_memsz)
567 bzero((void *)(phdr[i].p_vaddr - KERNVIRTADDR +
568 curaddr + phdr[i].p_filesz), phdr[i].p_memsz -
571 /* Now grab the symbol tables. */
572 if (symtabindex >= 0 && symstrindex >= 0) {
573 *(Elf_Size *)lastaddr =
574 shdr[symtabindex].sh_size;
575 lastaddr += sizeof(shdr[symtabindex].sh_size);
576 memcpy((void*)lastaddr,
578 shdr[symtabindex].sh_size);
579 lastaddr += shdr[symtabindex].sh_size;
580 lastaddr = roundup(lastaddr,
581 sizeof(shdr[symtabindex].sh_size));
582 *(Elf_Size *)lastaddr =
583 shdr[symstrindex].sh_size;
584 lastaddr += sizeof(shdr[symstrindex].sh_size);
585 memcpy((void*)lastaddr,
587 shdr[symtabindex].sh_size),
588 shdr[symstrindex].sh_size);
589 lastaddr += shdr[symstrindex].sh_size;
590 lastaddr = roundup(lastaddr,
591 sizeof(shdr[symstrindex].sh_size));
592 *(Elf_Addr *)curaddr = MAGIC_TRAMP_NUMBER;
593 *((Elf_Addr *)curaddr + 1) = ssym - curaddr + KERNVIRTADDR;
594 *((Elf_Addr *)curaddr + 2) = lastaddr - curaddr + KERNVIRTADDR;
596 *(Elf_Addr *)curaddr = 0;
597 /* Invalidate the instruction cache. */
598 __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n"
599 "mcr p15, 0, %0, c7, c10, 4\n"
601 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
602 "bic %0, %0, #1\n" /* MMU_ENABLE */
603 "mcr p15, 0, %0, c1, c0, 0\n"
605 /* Jump to the entry point. */
606 ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))();
607 __asm __volatile(".globl func_end\n"
614 extern char func_end[];
617 #define PMAP_DOMAIN_KERNEL 0 /*
618 * Just define it instead of including the
619 * whole VM headers set.
623 setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend,
626 unsigned int *pd = (unsigned int *)pt_addr;
628 int domain = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT;
631 bzero(pd, L1_TABLE_SIZE);
632 for (addr = physstart; addr < physend; addr += L1_S_SIZE) {
633 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)|
634 L1_S_DOM(PMAP_DOMAIN_KERNEL) | addr;
636 pd[addr >> L1_S_SHIFT] |= L1_S_B;
639 if (0xfff00000 < physstart || 0xfff00000 > physend)
640 pd[0xfff00000 >> L1_S_SHIFT] = L1_TYPE_S|L1_S_AP(AP_KRW)|
641 L1_S_DOM(PMAP_DOMAIN_KERNEL)|physstart;
642 __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */
643 "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */
644 "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */
645 "mrc p15, 0, %0, c1, c0, 0\n"
646 "orr %0, %0, #1\n" /* MMU_ENABLE */
647 "mcr p15, 0, %0, c1, c0, 0\n"
648 "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */
651 "=r" (tmp) : "r" (pd), "r" (domain));
654 * XXX: This is the most stupid workaround I've ever wrote.
655 * For some reason, the KB9202 won't boot the kernel unless
656 * we access an address which is not in the
657 * 0x20000000 - 0x20ffffff range. I hope I'll understand
658 * what's going on later.
660 __hack = *(volatile int *)0xfffff21c;
668 char *kernel = (char *)&kernel_start;
672 __asm __volatile("mov %0, pc" :
674 curaddr = (void*)((unsigned int)curaddr & 0xfff00000);
676 if (*kernel == 0x1f && kernel[1] == 0x8b) {
677 pt_addr = (((int)&_end + KERNSIZE + 0x100) &
678 ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
681 /* So that idcache_wbinv works; */
682 if ((cpufunc_id() & 0x0000f000) == 0x00009000)
685 setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
686 (vm_paddr_t)curaddr + 0x10000000, 1);
688 dst = inflate_kernel(kernel, &_end);
689 kernel = (char *)&_end;
690 altdst = 4 + load_kernel((unsigned int)kernel,
691 (unsigned int)curaddr,
692 (unsigned int)&func_end + 800 , 0);
697 * Disable MMU. Otherwise, setup_pagetables call below
698 * might overwrite the L1 table we are currently using.
700 cpu_idcache_wbinv_all();
701 cpu_l2cache_wbinv_all();
702 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
703 "bic %0, %0, #1\n" /* MMU_DISABLE */
704 "mcr p15, 0, %0, c1, c0, 0\n"
708 dst = 4 + load_kernel((unsigned int)&kernel_start,
709 (unsigned int)curaddr,
710 (unsigned int)&func_end, 0);
711 dst = (void *)(((vm_offset_t)dst & ~3));
712 pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
713 setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
714 (vm_paddr_t)curaddr + 0x10000000, 0);
715 sp = pt_addr + L1_TABLE_SIZE + 8192;
717 dst = (void *)(sp + 4);
718 memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end -
719 (unsigned int)&load_kernel + 800);
720 do_call(dst, kernel, dst + (unsigned int)(&func_end) -
721 (unsigned int)(&load_kernel) + 800, sp);
725 /* We need to provide these functions but never call them */
726 void __aeabi_unwind_cpp_pr0(void);
727 void __aeabi_unwind_cpp_pr1(void);
728 void __aeabi_unwind_cpp_pr2(void);
730 __strong_reference(__aeabi_unwind_cpp_pr0, __aeabi_unwind_cpp_pr1);
731 __strong_reference(__aeabi_unwind_cpp_pr0, __aeabi_unwind_cpp_pr2);
733 __aeabi_unwind_cpp_pr0(void)