1 /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */
4 * Copyright (c) 1994-1997 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
8 * This code is derived from software written for Brini by Mark Brinicombe
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * RiscBSD kernel project
41 * Low level handlers for exception vectors
45 * Based on kate/display/abort.s
51 #include <machine/asm.h>
52 #include <machine/armreg.h>
53 #include <machine/asmacros.h>
54 #include <machine/trap.h>
56 __FBSDID("$FreeBSD$");
61 .global _C_LABEL(dtrace_invop_jump_addr)
62 _C_LABEL(dtrace_invop_jump_addr):
71 * ASM macros for pushing and pulling trapframes from the stack
73 * These macros are used to handle the irqframe and trapframe structures
78 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
79 * Since the current mode is used, the SVC lr field is not defined.
82 sub sp, sp, #4; /* Align the stack */ \
83 str lr, [sp, #-4]!; /* Push the return address */ \
84 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
85 stmia sp, {r0-r12}; /* Push the user mode registers */ \
86 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
87 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
88 mov r0, r0; /* NOP for previous instruction */ \
89 mrs r0, spsr; /* Put the SPSR on the stack */ \
93 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
94 * Since the current mode is used, the SVC lr field is ignored.
98 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \
101 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
102 mov r0, r0; /* NOP for previous instruction */ \
103 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
104 ldr lr, [sp], #4; /* Pull the return address */ \
105 add sp, sp, #4 /* Align the stack */
108 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
109 * This should only be used if the processor is not currently in SVC32
110 * mode. The processor mode is switched to SVC mode and the trap frame is
111 * stored. The SVC lr field is used to store the previous value of
114 #define PUSHFRAMEINSVC \
115 stmdb sp, {r0-r3}; /* Save 4 registers */ \
116 mov r0, lr; /* Save xxx32 r14 */ \
117 mov r1, sp; /* Save xxx32 sp */ \
118 mrs r3, spsr; /* Save xxx32 spsr */ \
119 mrs r2, cpsr; /* Get the CPSR */ \
120 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
121 orr r2, r2, #(PSR_SVC32_MODE); \
122 msr cpsr_c, r2; /* Punch into SVC mode */ \
123 mov r2, sp; /* Save SVC sp */ \
124 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \
125 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \
126 /* and for dtrace to emulate push/pop */ \
127 str r0, [sp, #-4]!; /* Push return address */ \
128 str lr, [sp, #-4]!; /* Push SVC lr */ \
129 str r2, [sp, #-4]!; /* Push SVC sp */ \
130 msr spsr_fsxc, r3; /* Restore correct spsr */ \
131 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
132 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
133 stmia sp, {r0-r12}; /* Push the user mode registers */ \
134 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
135 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
136 mov r0, r0; /* NOP for previous instruction */ \
137 mrs r0, spsr; /* Put the SPSR on the stack */ \
141 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
142 * in SVC32 mode and restore the saved processor mode and PC.
143 * This should be used when the SVC lr register needs to be restored on
147 #define PULLFRAMEFROMSVCANDEXIT \
148 ldr r0, [sp], #4; /* Get the SPSR from stack */ \
149 msr spsr_fsxc, r0; /* restore SPSR */ \
151 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
152 mov r0, r0; /* NOP for previous instruction */ \
153 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
154 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
157 * Unwind hints so we can unwind past functions that use
158 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order.
159 * As the last thing we do is restore the stack pointer
160 * we can ignore the padding at the end of struct trapframe.
162 #define UNWINDSVCFRAME \
163 .save {r13-r15}; /* Restore sp, lr, pc */ \
164 .pad #(2*4); /* Skip user sp and lr */ \
165 .save {r0-r12}; /* Restore r0-r12 */ \
166 .pad #(4) /* Skip spsr */
169 ldr r0, [sp]; /* Get the SPSR from stack */ \
170 mrs r4, cpsr; /* save CPSR */ \
171 orr r1, r4, #(PSR_I|PSR_F); \
172 msr cpsr_c, r1; /* Disable interrupts */ \
173 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \
174 teq r0, #(PSR_USR32_MODE); \
175 bne 2f; /* Nope, get out now */ \
176 bic r4, r4, #(PSR_I|PSR_F); \
177 1: GET_CURTHREAD_PTR(r5); \
178 ldr r1, [r5, #(TD_AST)]; \
180 beq 2f; /* Nope. Just bail */ \
181 msr cpsr_c, r4; /* Restore interrupts */ \
183 bl _C_LABEL(ast); /* ast(frame) */ \
184 orr r0, r4, #(PSR_I|PSR_F); \
191 * Entry point for a Software Interrupt (SWI).
193 * The hardware switches to svc32 mode on a swi, so we're already on the
194 * right stack; just build a trapframe and call the handler.
196 ASENTRY_NP(swi_entry)
197 PUSHFRAME /* Build the trapframe on the */
198 mov r0, sp /* scv32 stack, pass it to the */
199 bl _C_LABEL(swi_handler) /* swi handler. */
201 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit()
202 * to return to swi_exit here, to return to userland. The net effect is
203 * that a newly created thread appears to return from a SWI just like
204 * the parent thread that created it.
206 ASEENTRY_NP(swi_exit)
207 DO_AST /* Handle pending signals. */
208 PULLFRAME /* Deallocate trapframe. */
209 movs pc, lr /* Return to userland. */
210 STOP_UNWINDING /* Don't unwind into user mode. */
215 * Standard exception exit handler.
217 * This is used to return from all exceptions except SWI. It uses DO_AST and
218 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code
219 * used PUSHFRAMEINSVC.
221 * If the return is to user mode, this uses DO_AST to deliver any pending
222 * signals and/or handle TDF_NEEDRESCHED first.
224 ASENTRY_NP(exception_exit)
225 DO_AST /* Handle pending signals. */
226 PULLFRAMEFROMSVCANDEXIT /* Return. */
227 UNWINDSVCFRAME /* Special unwinding for exceptions. */
231 * Entry point for a Prefetch Abort exception.
233 * The hardware switches to the abort mode stack; we switch to svc32 before
234 * calling the handler, then return directly to the original mode/stack
235 * on exit (without transitioning back through the abort mode stack).
237 ASENTRY_NP(prefetch_abort_entry)
238 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */
239 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
240 adr lr, exception_exit /* Return from handler via standard */
241 mov r0, sp /* exception exit routine. Pass the */
242 mov r1, #1 /* Type flag */
243 b _C_LABEL(abort_handler)
244 END(prefetch_abort_entry)
247 * Entry point for a Data Abort exception.
249 * The hardware switches to the abort mode stack; we switch to svc32 before
250 * calling the handler, then return directly to the original mode/stack
251 * on exit (without transitioning back through the abort mode stack).
253 ASENTRY_NP(data_abort_entry)
254 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */
255 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
256 adr lr, exception_exit /* Exception exit routine */
257 mov r0, sp /* Trapframe to the handler */
258 mov r1, #0 /* Type flag */
259 b _C_LABEL(abort_handler)
260 END(data_abort_entry)
263 * Entry point for an Undefined Instruction exception.
265 * The hardware switches to the undefined mode stack; we switch to svc32 before
266 * calling the handler, then return directly to the original mode/stack
267 * on exit (without transitioning back through the undefined mode stack).
269 ASENTRY_NP(undefined_entry)
270 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
271 mov r4, r0 /* R0 contains SPSR */
272 adr lr, exception_exit /* Return from handler via standard */
273 mov r0, sp /* exception exit routine. pass frame */
275 ldr r2, [sp, #(TF_PC)] /* load pc */
277 tst r4, #(PSR_T) /* test if PSR_T */
278 subne r2, r2, #(THUMB_INSN_SIZE)
279 subeq r2, r2, #(INSN_SIZE)
281 sub r2, r2, #(INSN_SIZE) /* fix pc */
283 str r2, [sp, #TF_PC] /* store pc */
286 /* Check if dtrace is enabled */
287 ldr r1, =_C_LABEL(dtrace_invop_jump_addr)
290 beq undefinedinstruction
292 and r4, r4, #(PSR_MODE) /* Mask out unneeded bits */
293 cmp r4, #(PSR_USR32_MODE) /* Check if we came from usermode */
294 beq undefinedinstruction
296 ldr r4, [r2] /* load instrution */
297 ldr r1, =FBT_BREAKPOINT /* load fbt inv op */
299 bne undefinedinstruction
301 bx r3 /* call invop_jump_addr */
303 b undefinedinstruction /* call stadnard handler */
307 * Entry point for a normal IRQ.
309 * The hardware switches to the IRQ mode stack; we switch to svc32 before
310 * calling the handler, then return directly to the original mode/stack
311 * on exit (without transitioning back through the IRQ mode stack).
313 ASENTRY_NP(irq_entry)
314 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */
315 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
316 adr lr, exception_exit /* Return from handler via standard */
317 mov r0, sp /* exception exit routine. Pass the */
318 b _C_LABEL(intr_irq_handler)/* trapframe to the handler. */
322 * Entry point for an FIQ interrupt.
324 * We don't currently support FIQ handlers very much. Something can
325 * install itself in the FIQ vector using code (that may or may not work
326 * these days) in fiq.c. If nobody does that and an FIQ happens, this
327 * default handler just disables FIQs and otherwise ignores it.
329 ASENTRY_NP(fiq_entry)
330 mrs r8, cpsr /* FIQ handling isn't supported, */
331 bic r8, #(PSR_F) /* just disable FIQ and return. */
332 msr cpsr_c, r8 /* The r8 we trash here is the */
333 subs pc, lr, #4 /* banked FIQ-mode r8. */
337 * Entry point for an Address Exception exception.
338 * This is an arm26 exception that should never happen.
340 ASENTRY_NP(addr_exception_entry)
344 adr r0, Laddr_exception_msg
347 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
349 END(addr_exception_entry)
352 * Entry point for the system Reset vector.
353 * This should never happen, so panic.
355 ASENTRY_NP(reset_entry)
357 adr r0, Lreset_panicmsg
361 .asciz "Reset vector called, LR = 0x%08x"
366 * page0 and page0_data -- An image of the ARM vectors which is copied to
367 * the ARM vectors page (high or low) as part of CPU initialization. The
368 * code that does the copy assumes that page0_data holds one 32-bit word
369 * of data for each of the predefined ARM vectors. It also assumes that
370 * page0_data follows the vectors in page0, but other stuff can appear
371 * between the two. We currently leave room between the two for some fiq
372 * handler code to be copied in.
374 .global _C_LABEL(page0), _C_LABEL(page0_data)
377 ldr pc, .Lreset_entry
378 ldr pc, .Lundefined_entry
380 ldr pc, .Lprefetch_abort_entry
381 ldr pc, .Ldata_abort_entry
382 ldr pc, .Laddr_exception_entry
384 .fiqv: ldr pc, .Lfiq_entry
385 .space 256 /* room for some fiq handler code */
387 _C_LABEL(page0_data):
388 .Lreset_entry: .word reset_entry
389 .Lundefined_entry: .word undefined_entry
390 .Lswi_entry: .word swi_entry
391 .Lprefetch_abort_entry: .word prefetch_abort_entry
392 .Ldata_abort_entry: .word data_abort_entry
393 .Laddr_exception_entry: .word addr_exception_entry
394 .Lirq_entry: .word irq_entry
395 .Lfiq_entry: .word fiq_entry
398 * These items are used by the code in fiq.c to install what it calls the
399 * "null" handler. It's actually our default vector entry that just jumps
400 * to the default handler which just disables FIQs and returns.
402 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size)
404 _C_LABEL(fiq_nullhandler_code):
406 _C_LABEL(fiq_nullhandler_size):