1 /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */
4 * Copyright (c) 1994-1997 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
8 * This code is derived from software written for Brini by Mark Brinicombe
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * RiscBSD kernel project
41 * Low level handlers for exception vectors
45 * Based on kate/display/abort.s
51 #include <machine/acle-compat.h>
52 #include <machine/asm.h>
53 #include <machine/armreg.h>
54 #include <machine/asmacros.h>
55 __FBSDID("$FreeBSD$");
60 .global _C_LABEL(dtrace_invop_calltrap_addr)
61 _C_LABEL(dtrace_invop_calltrap_addr):
70 * ASM macros for pushing and pulling trapframes from the stack
72 * These macros are used to handle the irqframe and trapframe structures
77 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
78 * Since the current mode is used, the SVC lr field is not defined.
80 * NOTE: r13 and r14 are stored separately as a work around for the
81 * SA110 rev 2 STM^ bug
85 sub sp, sp, #4; /* Align the stack */ \
86 str lr, [sp, #-4]!; /* Push the return address */ \
87 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
88 stmia sp, {r0-r12}; /* Push the user mode registers */ \
89 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
90 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
91 mov r0, r0; /* NOP for previous instruction */ \
92 mrs r0, spsr; /* Put the SPSR on the stack */ \
94 ldr r0, =ARM_RAS_START; \
97 mov r1, #0xffffffff; \
101 sub sp, sp, #4; /* Align the stack */ \
102 str lr, [sp, #-4]!; /* Push the return address */ \
103 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
104 stmia sp, {r0-r12}; /* Push the user mode registers */ \
105 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
106 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
107 mov r0, r0; /* NOP for previous instruction */ \
108 mrs r0, spsr; /* Put the SPSR on the stack */ \
113 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
114 * Since the current mode is used, the SVC lr field is ignored.
119 ldr r0, [sp], #4; /* Get the SPSR from stack */ \
121 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
122 mov r0, r0; /* NOP for previous instruction */ \
123 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
124 ldr lr, [sp], #4; /* Pull the return address */ \
125 add sp, sp, #4 /* Align the stack */
128 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \
131 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
132 mov r0, r0; /* NOP for previous instruction */ \
133 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
134 ldr lr, [sp], #4; /* Pull the return address */ \
135 add sp, sp, #4 /* Align the stack */
139 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
140 * This should only be used if the processor is not currently in SVC32
141 * mode. The processor mode is switched to SVC mode and the trap frame is
142 * stored. The SVC lr field is used to store the previous value of
145 * NOTE: r13 and r14 are stored separately as a work around for the
146 * SA110 rev 2 STM^ bug
149 #define PUSHFRAMEINSVC \
150 stmdb sp, {r0-r3}; /* Save 4 registers */ \
151 mov r0, lr; /* Save xxx32 r14 */ \
152 mov r1, sp; /* Save xxx32 sp */ \
153 mrs r3, spsr; /* Save xxx32 spsr */ \
154 mrs r2, cpsr; /* Get the CPSR */ \
155 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
156 orr r2, r2, #(PSR_SVC32_MODE); \
157 msr cpsr_c, r2; /* Punch into SVC mode */ \
158 mov r2, sp; /* Save SVC sp */ \
159 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \
160 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \
161 /* and for dtrace to emulate push/pop */ \
162 str r0, [sp, #-4]!; /* Push return address */ \
163 str lr, [sp, #-4]!; /* Push SVC lr */ \
164 str r2, [sp, #-4]!; /* Push SVC sp */ \
165 msr spsr_fsxc, r3; /* Restore correct spsr */ \
166 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
167 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
168 stmia sp, {r0-r12}; /* Push the user mode registers */ \
169 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
170 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
171 mov r0, r0; /* NOP for previous instruction */ \
172 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \
173 ldr r4, [r5, #4]; /* reset it to point at the */ \
174 cmp r4, #0xffffffff; /* end of memory if necessary; */ \
175 movne r1, #0xffffffff; /* leave value in r4 for later */ \
176 strne r1, [r5, #4]; /* comparision against PC. */ \
177 ldr r3, [r5]; /* Retrieve global RAS_START */ \
178 cmp r3, #0; /* and reset it if non-zero. */ \
179 movne r1, #0; /* If non-zero RAS_START and */ \
180 strne r1, [r5]; /* PC was lower than RAS_END, */ \
181 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \
182 cmpne r4, r1; /* execution later resumes at */ \
183 strhi r3, [r0, #16]; /* the RAS_START location. */ \
187 #define PUSHFRAMEINSVC \
188 stmdb sp, {r0-r3}; /* Save 4 registers */ \
189 mov r0, lr; /* Save xxx32 r14 */ \
190 mov r1, sp; /* Save xxx32 sp */ \
191 mrs r3, spsr; /* Save xxx32 spsr */ \
192 mrs r2, cpsr; /* Get the CPSR */ \
193 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
194 orr r2, r2, #(PSR_SVC32_MODE); \
195 msr cpsr_c, r2; /* Punch into SVC mode */ \
196 mov r2, sp; /* Save SVC sp */ \
197 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \
198 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \
199 /* and for dtrace to emulate push/pop */ \
200 str r0, [sp, #-4]!; /* Push return address */ \
201 str lr, [sp, #-4]!; /* Push SVC lr */ \
202 str r2, [sp, #-4]!; /* Push SVC sp */ \
203 msr spsr_fsxc, r3; /* Restore correct spsr */ \
204 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
205 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
206 stmia sp, {r0-r12}; /* Push the user mode registers */ \
207 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
208 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
209 mov r0, r0; /* NOP for previous instruction */ \
210 mrs r0, spsr; /* Put the SPSR on the stack */ \
215 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
216 * in SVC32 mode and restore the saved processor mode and PC.
217 * This should be used when the SVC lr register needs to be restored on
222 #define PULLFRAMEFROMSVCANDEXIT \
223 ldr r0, [sp], #4; /* Get the SPSR from stack */ \
224 msr spsr_fsxc, r0; /* restore SPSR */ \
225 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
226 mov r0, r0; /* NOP for previous instruction */ \
227 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
228 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
230 #define PULLFRAMEFROMSVCANDEXIT \
231 ldr r0, [sp], #4; /* Get the SPSR from stack */ \
232 msr spsr_fsxc, r0; /* restore SPSR */ \
234 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
235 mov r0, r0; /* NOP for previous instruction */ \
236 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
237 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
241 * Unwind hints so we can unwind past functions that use
242 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order.
243 * As the last thing we do is restore the stack pointer
244 * we can ignore the padding at the end of struct trapframe.
246 #define UNWINDSVCFRAME \
247 .save {r13-r15}; /* Restore sp, lr, pc */ \
248 .pad #(2*4); /* Skip user sp and lr */ \
249 .save {r0-r12}; /* Restore r0-r12 */ \
250 .pad #(4) /* Skip spsr */
253 ldr r0, [sp]; /* Get the SPSR from stack */ \
254 mrs r4, cpsr; /* save CPSR */ \
255 orr r1, r4, #(PSR_I|PSR_F); \
256 msr cpsr_c, r1; /* Disable interrupts */ \
257 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \
258 teq r0, #(PSR_USR32_MODE); \
259 bne 2f; /* Nope, get out now */ \
260 bic r4, r4, #(PSR_I|PSR_F); \
261 1: GET_CURTHREAD_PTR(r5); \
262 ldr r1, [r5, #(TD_FLAGS)]; \
263 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED); \
265 beq 2f; /* Nope. Just bail */ \
266 msr cpsr_c, r4; /* Restore interrupts */ \
268 bl _C_LABEL(ast); /* ast(frame) */ \
269 orr r0, r4, #(PSR_I|PSR_F); \
276 * Entry point for a Software Interrupt (SWI).
278 * The hardware switches to svc32 mode on a swi, so we're already on the
279 * right stack; just build a trapframe and call the handler.
281 ASENTRY_NP(swi_entry)
282 PUSHFRAME /* Build the trapframe on the */
283 mov r0, sp /* scv32 stack, pass it to the */
284 bl _C_LABEL(swi_handler) /* swi handler. */
286 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit()
287 * to return to swi_exit here, to return to userland. The net effect is
288 * that a newly created thread appears to return from a SWI just like
289 * the parent thread that created it.
291 ASEENTRY_NP(swi_exit)
292 DO_AST /* Handle pending signals. */
293 PULLFRAME /* Deallocate trapframe. */
294 movs pc, lr /* Return to userland. */
295 STOP_UNWINDING /* Don't unwind into user mode. */
300 * Standard exception exit handler.
302 * This is used to return from all exceptions except SWI. It uses DO_AST and
303 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code
304 * used PUSHFRAMEINSVC.
306 * If the return is to user mode, this uses DO_AST to deliver any pending
307 * signals and/or handle TDF_NEEDRESCHED first.
309 ASENTRY_NP(exception_exit)
310 DO_AST /* Handle pending signals. */
311 PULLFRAMEFROMSVCANDEXIT /* Return. */
312 UNWINDSVCFRAME /* Special unwinding for exceptions. */
316 * Entry point for a Prefetch Abort exception.
318 * The hardware switches to the abort mode stack; we switch to svc32 before
319 * calling the handler, then return directly to the original mode/stack
320 * on exit (without transitioning back through the abort mode stack).
322 ASENTRY_NP(prefetch_abort_entry)
324 nop /* Make absolutely sure any pending */
325 nop /* imprecise aborts have occurred. */
327 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */
328 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
329 adr lr, exception_exit /* Return from handler via standard */
330 mov r0, sp /* exception exit routine. Pass the */
331 mov r1, #1 /* Type flag */
332 b _C_LABEL(abort_handler)
333 END(prefetch_abort_entry)
336 * Entry point for a Data Abort exception.
338 * The hardware switches to the abort mode stack; we switch to svc32 before
339 * calling the handler, then return directly to the original mode/stack
340 * on exit (without transitioning back through the abort mode stack).
342 ASENTRY_NP(data_abort_entry)
344 nop /* Make absolutely sure any pending */
345 nop /* imprecise aborts have occurred. */
347 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */
348 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
349 adr lr, exception_exit /* Exception exit routine */
350 mov r0, sp /* Trapframe to the handler */
351 mov r1, #0 /* Type flag */
352 b _C_LABEL(abort_handler)
353 END(data_abort_entry)
356 * Entry point for an Undefined Instruction exception.
358 * The hardware switches to the undefined mode stack; we switch to svc32 before
359 * calling the handler, then return directly to the original mode/stack
360 * on exit (without transitioning back through the undefined mode stack).
362 ASENTRY_NP(undefined_entry)
363 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
364 adr lr, exception_exit /* Return from handler via standard */
365 mov r0, sp /* exception exit routine. Pass the */
366 b undefinedinstruction /* trapframe to the handler. */
370 * Entry point for a normal IRQ.
372 * The hardware switches to the IRQ mode stack; we switch to svc32 before
373 * calling the handler, then return directly to the original mode/stack
374 * on exit (without transitioning back through the IRQ mode stack).
376 ASENTRY_NP(irq_entry)
377 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */
378 PUSHFRAMEINSVC /* mode stack, build trapframe there. */
379 adr lr, exception_exit /* Return from handler via standard */
380 mov r0, sp /* exception exit routine. Pass the */
381 b _C_LABEL(arm_irq_handler)/* trapframe to the handler. */
385 * Entry point for an FIQ interrupt.
387 * We don't currently support FIQ handlers very much. Something can
388 * install itself in the FIQ vector using code (that may or may not work
389 * these days) in fiq.c. If nobody does that and an FIQ happens, this
390 * default handler just disables FIQs and otherwise ignores it.
392 ASENTRY_NP(fiq_entry)
393 mrs r8, cpsr /* FIQ handling isn't supported, */
394 bic r8, #(PSR_F) /* just disable FIQ and return. */
395 msr cpsr_c, r8 /* The r8 we trash here is the */
396 subs pc, lr, #4 /* banked FIQ-mode r8. */
400 * Entry point for an Address Exception exception.
401 * This is an arm26 exception that should never happen.
403 ASENTRY_NP(addr_exception_entry)
407 adr r0, Laddr_exception_msg
410 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
412 END(addr_exception_entry)
415 * Entry point for the system Reset vector.
416 * This should never happen, so panic.
418 ASENTRY_NP(reset_entry)
420 adr r0, Lreset_panicmsg
424 .asciz "Reset vector called, LR = 0x%08x"
429 * page0 and page0_data -- An image of the ARM vectors which is copied to
430 * the ARM vectors page (high or low) as part of CPU initialization. The
431 * code that does the copy assumes that page0_data holds one 32-bit word
432 * of data for each of the predefined ARM vectors. It also assumes that
433 * page0_data follows the vectors in page0, but other stuff can appear
434 * between the two. We currently leave room between the two for some fiq
435 * handler code to be copied in.
437 .global _C_LABEL(page0), _C_LABEL(page0_data)
440 ldr pc, .Lreset_entry
441 ldr pc, .Lundefined_entry
443 ldr pc, .Lprefetch_abort_entry
444 ldr pc, .Ldata_abort_entry
445 ldr pc, .Laddr_exception_entry
447 .fiqv: ldr pc, .Lfiq_entry
448 .space 256 /* room for some fiq handler code */
450 _C_LABEL(page0_data):
451 .Lreset_entry: .word reset_entry
452 .Lundefined_entry: .word undefined_entry
453 .Lswi_entry: .word swi_entry
454 .Lprefetch_abort_entry: .word prefetch_abort_entry
455 .Ldata_abort_entry: .word data_abort_entry
456 .Laddr_exception_entry: .word addr_exception_entry
457 .Lirq_entry: .word irq_entry
458 .Lfiq_entry: .word fiq_entry
461 * These items are used by the code in fiq.c to install what it calls the
462 * "null" handler. It's actually our default vector entry that just jumps
463 * to the default handler which just disables FIQs and returns.
465 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size)
467 _C_LABEL(fiq_nullhandler_code):
469 _C_LABEL(fiq_nullhandler_size):