2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
38 #include "opt_platform.h"
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/malloc.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
52 #include <sys/watchdog.h>
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/intr.h>
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/openfirm.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
65 #include <contrib/dev/acpica/include/acpi.h>
66 #include <dev/acpica/acpivar.h>
69 #define GT_CTRL_ENABLE (1 << 0)
70 #define GT_CTRL_INT_MASK (1 << 1)
71 #define GT_CTRL_INT_STAT (1 << 2)
75 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
76 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
77 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
78 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
79 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
80 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
81 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
83 struct arm_tmr_softc {
84 struct resource *res[4];
91 static struct arm_tmr_softc *arm_tmr_sc = NULL;
93 static struct resource_spec timer_spec[] = {
94 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
95 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
96 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* Virt */
97 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
101 static timecounter_get_t arm_tmr_get_timecount;
103 static struct timecounter arm_tmr_timecount = {
104 .tc_name = "ARM MPCore Timecounter",
105 .tc_get_timecount = arm_tmr_get_timecount,
107 .tc_counter_mask = ~0u,
113 #define get_el0(x) cp15_## x ##_get()
114 #define get_el1(x) cp15_## x ##_get()
115 #define set_el0(x, val) cp15_## x ##_set(val)
116 #define set_el1(x, val) cp15_## x ##_set(val)
117 #else /* __aarch64__ */
118 #define get_el0(x) READ_SPECIALREG(x ##_el0)
119 #define get_el1(x) READ_SPECIALREG(x ##_el1)
120 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
121 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
127 return (get_el0(cntfrq));
131 get_cntxct(bool physical)
137 val = get_el0(cntpct);
139 val = get_el0(cntvct);
145 set_ctrl(uint32_t val, bool physical)
149 set_el0(cntp_ctl, val);
151 set_el0(cntv_ctl, val);
158 set_tval(uint32_t val, bool physical)
162 set_el0(cntp_tval, val);
164 set_el0(cntv_tval, val);
171 get_ctrl(bool physical)
176 val = get_el0(cntp_ctl);
178 val = get_el0(cntv_ctl);
184 disable_user_access(void)
188 cntkctl = get_el1(cntkctl);
189 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
190 GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
191 set_el1(cntkctl, cntkctl);
196 arm_tmr_get_timecount(struct timecounter *tc)
199 return (get_cntxct(arm_tmr_sc->physical));
203 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
205 struct arm_tmr_softc *sc;
208 sc = (struct arm_tmr_softc *)et->et_priv;
211 counts = ((uint32_t)et->et_frequency * first) >> 32;
212 ctrl = get_ctrl(sc->physical);
213 ctrl &= ~GT_CTRL_INT_MASK;
214 ctrl |= GT_CTRL_ENABLE;
215 set_tval(counts, sc->physical);
216 set_ctrl(ctrl, sc->physical);
225 arm_tmr_stop(struct eventtimer *et)
227 struct arm_tmr_softc *sc;
230 sc = (struct arm_tmr_softc *)et->et_priv;
232 ctrl = get_ctrl(sc->physical);
233 ctrl &= GT_CTRL_ENABLE;
234 set_ctrl(ctrl, sc->physical);
240 arm_tmr_intr(void *arg)
242 struct arm_tmr_softc *sc;
245 sc = (struct arm_tmr_softc *)arg;
246 ctrl = get_ctrl(sc->physical);
247 if (ctrl & GT_CTRL_INT_STAT) {
248 ctrl |= GT_CTRL_INT_MASK;
249 set_ctrl(ctrl, sc->physical);
252 if (sc->et.et_active)
253 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
255 return (FILTER_HANDLED);
260 arm_tmr_fdt_probe(device_t dev)
263 if (!ofw_bus_status_okay(dev))
266 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
267 device_set_desc(dev, "ARMv7 Generic Timer");
268 return (BUS_PROBE_DEFAULT);
269 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
270 device_set_desc(dev, "ARMv8 Generic Timer");
271 return (BUS_PROBE_DEFAULT);
280 arm_tmr_acpi_identify(driver_t *driver, device_t parent)
282 ACPI_TABLE_GTDT *gtdt;
286 physaddr = acpi_find_table(ACPI_SIG_GTDT);
290 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT);
292 device_printf(parent, "gic: Unable to map the GTDT\n");
296 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE,
297 "generic_timer", -1);
299 device_printf(parent, "add gic child failed\n");
303 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 0,
304 gtdt->SecureEl1Interrupt, 1);
305 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 1,
306 gtdt->NonSecureEl1Interrupt, 1);
307 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 2,
308 gtdt->VirtualTimerInterrupt, 1);
311 acpi_unmap_table(gtdt);
315 arm_tmr_acpi_probe(device_t dev)
318 device_set_desc(dev, "ARM Generic Timer");
319 return (BUS_PROBE_NOWILDCARD);
325 arm_tmr_attach(device_t dev)
327 struct arm_tmr_softc *sc;
335 sc = device_get_softc(dev);
340 /* Get the base clock frequency */
341 node = ofw_bus_get_node(dev);
343 error = OF_getprop(node, "clock-frequency", &clock,
346 sc->clkfreq = fdt32_to_cpu(clock);
351 if (sc->clkfreq == 0) {
352 /* Try to get clock frequency from timer */
353 sc->clkfreq = get_freq();
356 if (sc->clkfreq == 0) {
357 device_printf(dev, "No clock frequency specified\n");
361 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
362 device_printf(dev, "could not allocate resources\n");
368 #else /* __aarch64__ */
369 sc->physical = false;
374 /* Setup secure, non-secure and virtual IRQs handler */
375 for (i = 0; i < 3; i++) {
376 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
377 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
379 device_printf(dev, "Unable to alloc int resource.\n");
384 disable_user_access();
386 arm_tmr_timecount.tc_frequency = sc->clkfreq;
387 tc_init(&arm_tmr_timecount);
389 sc->et.et_name = "ARM MPCore Eventtimer";
390 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
391 sc->et.et_quality = 1000;
393 sc->et.et_frequency = sc->clkfreq;
394 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
395 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
396 sc->et.et_start = arm_tmr_start;
397 sc->et.et_stop = arm_tmr_stop;
399 et_register(&sc->et);
405 static device_method_t arm_tmr_fdt_methods[] = {
406 DEVMETHOD(device_probe, arm_tmr_fdt_probe),
407 DEVMETHOD(device_attach, arm_tmr_attach),
411 static driver_t arm_tmr_fdt_driver = {
414 sizeof(struct arm_tmr_softc),
417 static devclass_t arm_tmr_fdt_devclass;
419 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
420 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
421 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
422 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
426 static device_method_t arm_tmr_acpi_methods[] = {
427 DEVMETHOD(device_identify, arm_tmr_acpi_identify),
428 DEVMETHOD(device_probe, arm_tmr_acpi_probe),
429 DEVMETHOD(device_attach, arm_tmr_attach),
433 static driver_t arm_tmr_acpi_driver = {
435 arm_tmr_acpi_methods,
436 sizeof(struct arm_tmr_softc),
439 static devclass_t arm_tmr_acpi_devclass;
441 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass,
442 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
448 int32_t counts, counts_per_usec;
449 uint32_t first, last;
452 * Check the timers are setup, if not just
453 * use a for loop for the meantime
455 if (arm_tmr_sc == NULL) {
456 for (; usec > 0; usec--)
457 for (counts = 200; counts > 0; counts--)
459 * Prevent the compiler from optimizing
466 /* Get the number of times to count */
467 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
470 * Clamp the timeout at a maximum value (about 32 seconds with
471 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
472 * near that length of time and if they are, they should be hung
475 if (usec >= (0x80000000U / counts_per_usec))
476 counts = (0x80000000U / counts_per_usec) - 1;
478 counts = usec * counts_per_usec;
480 first = get_cntxct(arm_tmr_sc->physical);
483 last = get_cntxct(arm_tmr_sc->physical);
484 counts -= (int32_t)(last - first);