2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2011 The FreeBSD Foundation
5 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
8 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the company nor the name of the author may be used to
19 * endorse or promote products derived from this software without specific
20 * prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
40 #include "opt_platform.h"
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/malloc.h>
52 #include <sys/timeet.h>
53 #include <sys/timetc.h>
56 #include <sys/watchdog.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60 #include <machine/md_var.h>
63 #include <machine/machdep.h> /* For arm_set_delay */
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
73 #include <contrib/dev/acpica/include/acpi.h>
74 #include <dev/acpica/acpivar.h>
75 #include "acpi_bus_if.h"
78 #define GT_CTRL_ENABLE (1 << 0)
79 #define GT_CTRL_INT_MASK (1 << 1)
80 #define GT_CTRL_INT_STAT (1 << 2)
84 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
85 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
86 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
87 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
88 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
89 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
90 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
92 struct arm_tmr_softc {
93 struct resource *res[4];
95 uint64_t (*get_cntxct)(bool);
101 static struct arm_tmr_softc *arm_tmr_sc = NULL;
103 static struct resource_spec timer_spec[] = {
104 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
105 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
106 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, /* Virt */
107 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
111 static uint32_t arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
112 struct timecounter *tc);
113 static void arm_tmr_do_delay(int usec, void *);
115 static timecounter_get_t arm_tmr_get_timecount;
117 static struct timecounter arm_tmr_timecount = {
118 .tc_name = "ARM MPCore Timecounter",
119 .tc_get_timecount = arm_tmr_get_timecount,
121 .tc_counter_mask = ~0u,
124 .tc_fill_vdso_timehands = arm_tmr_fill_vdso_timehands,
128 #define get_el0(x) cp15_## x ##_get()
129 #define get_el1(x) cp15_## x ##_get()
130 #define set_el0(x, val) cp15_## x ##_set(val)
131 #define set_el1(x, val) cp15_## x ##_set(val)
132 #else /* __aarch64__ */
133 #define get_el0(x) READ_SPECIALREG(x ##_el0)
134 #define get_el1(x) READ_SPECIALREG(x ##_el1)
135 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
136 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
142 return (get_el0(cntfrq));
146 get_cntxct_a64_unstable(bool physical)
153 val = get_el0(cntpct);
155 while (((val + 1) & 0x7FF) <= 1);
159 val = get_el0(cntvct);
161 while (((val + 1) & 0x7FF) <= 1);
168 get_cntxct(bool physical)
174 val = get_el0(cntpct);
176 val = get_el0(cntvct);
182 set_ctrl(uint32_t val, bool physical)
186 set_el0(cntp_ctl, val);
188 set_el0(cntv_ctl, val);
195 set_tval(uint32_t val, bool physical)
199 set_el0(cntp_tval, val);
201 set_el0(cntv_tval, val);
208 get_ctrl(bool physical)
213 val = get_el0(cntp_ctl);
215 val = get_el0(cntv_ctl);
221 setup_user_access(void *arg __unused)
225 cntkctl = get_el1(cntkctl);
226 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
228 if (arm_tmr_sc->physical) {
229 cntkctl |= GT_CNTKCTL_PL0PCTEN;
230 cntkctl &= ~GT_CNTKCTL_PL0VCTEN;
232 cntkctl |= GT_CNTKCTL_PL0VCTEN;
233 cntkctl &= ~GT_CNTKCTL_PL0PCTEN;
235 set_el1(cntkctl, cntkctl);
240 tmr_setup_user_access(void *arg __unused)
243 if (arm_tmr_sc != NULL)
244 smp_rendezvous(NULL, setup_user_access, NULL, NULL);
246 SYSINIT(tmr_ua, SI_SUB_SMP, SI_ORDER_ANY, tmr_setup_user_access, NULL);
249 arm_tmr_get_timecount(struct timecounter *tc)
252 return (arm_tmr_sc->get_cntxct(arm_tmr_sc->physical));
256 arm_tmr_start(struct eventtimer *et, sbintime_t first,
257 sbintime_t period __unused)
259 struct arm_tmr_softc *sc;
262 sc = (struct arm_tmr_softc *)et->et_priv;
265 counts = ((uint32_t)et->et_frequency * first) >> 32;
266 ctrl = get_ctrl(sc->physical);
267 ctrl &= ~GT_CTRL_INT_MASK;
268 ctrl |= GT_CTRL_ENABLE;
269 set_tval(counts, sc->physical);
270 set_ctrl(ctrl, sc->physical);
279 arm_tmr_disable(bool physical)
283 ctrl = get_ctrl(physical);
284 ctrl &= ~GT_CTRL_ENABLE;
285 set_ctrl(ctrl, physical);
289 arm_tmr_stop(struct eventtimer *et)
291 struct arm_tmr_softc *sc;
293 sc = (struct arm_tmr_softc *)et->et_priv;
294 arm_tmr_disable(sc->physical);
300 arm_tmr_intr(void *arg)
302 struct arm_tmr_softc *sc;
305 sc = (struct arm_tmr_softc *)arg;
306 ctrl = get_ctrl(sc->physical);
307 if (ctrl & GT_CTRL_INT_STAT) {
308 ctrl |= GT_CTRL_INT_MASK;
309 set_ctrl(ctrl, sc->physical);
312 if (sc->et.et_active)
313 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
315 return (FILTER_HANDLED);
320 arm_tmr_fdt_probe(device_t dev)
323 if (!ofw_bus_status_okay(dev))
326 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
327 device_set_desc(dev, "ARMv7 Generic Timer");
328 return (BUS_PROBE_DEFAULT);
329 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
330 device_set_desc(dev, "ARMv8 Generic Timer");
331 return (BUS_PROBE_DEFAULT);
340 arm_tmr_acpi_add_irq(device_t parent, device_t dev, int rid, u_int irq)
343 irq = ACPI_BUS_MAP_INTR(parent, dev, irq,
344 INTR_TRIGGER_LEVEL, INTR_POLARITY_HIGH);
345 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, rid, irq, 1);
349 arm_tmr_acpi_identify(driver_t *driver, device_t parent)
351 ACPI_TABLE_GTDT *gtdt;
355 physaddr = acpi_find_table(ACPI_SIG_GTDT);
359 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT);
361 device_printf(parent, "gic: Unable to map the GTDT\n");
365 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE,
366 "generic_timer", -1);
368 device_printf(parent, "add gic child failed\n");
372 arm_tmr_acpi_add_irq(parent, dev, 0, gtdt->SecureEl1Interrupt);
373 arm_tmr_acpi_add_irq(parent, dev, 1, gtdt->NonSecureEl1Interrupt);
374 arm_tmr_acpi_add_irq(parent, dev, 2, gtdt->VirtualTimerInterrupt);
377 acpi_unmap_table(gtdt);
381 arm_tmr_acpi_probe(device_t dev)
384 device_set_desc(dev, "ARM Generic Timer");
385 return (BUS_PROBE_NOWILDCARD);
391 arm_tmr_attach(device_t dev)
393 struct arm_tmr_softc *sc;
401 sc = device_get_softc(dev);
405 sc->get_cntxct = &get_cntxct;
407 /* Get the base clock frequency */
408 node = ofw_bus_get_node(dev);
410 error = OF_getencprop(node, "clock-frequency", &clock,
415 if (OF_hasprop(node, "allwinner,sun50i-a64-unstable-timer")) {
416 sc->get_cntxct = &get_cntxct_a64_unstable;
419 "Enabling allwinner unstable timer workaround\n");
424 if (sc->clkfreq == 0) {
425 /* Try to get clock frequency from timer */
426 sc->clkfreq = get_freq();
429 if (sc->clkfreq == 0) {
430 device_printf(dev, "No clock frequency specified\n");
434 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
435 device_printf(dev, "could not allocate resources\n");
441 #else /* __aarch64__ */
442 /* If we do not have a virtual timer use the physical. */
443 sc->physical = (sc->res[2] == NULL) ? true : false;
448 /* Setup secure, non-secure and virtual IRQs handler */
449 for (i = 0; i < 3; i++) {
450 /* If we do not have the interrupt, skip it. */
451 if (sc->res[i] == NULL)
453 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
454 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
456 device_printf(dev, "Unable to alloc int resource.\n");
461 /* Disable the virtual timer until we are ready */
462 if (sc->res[2] != NULL)
463 arm_tmr_disable(false);
464 /* And the physical */
466 arm_tmr_disable(true);
468 arm_tmr_timecount.tc_frequency = sc->clkfreq;
469 tc_init(&arm_tmr_timecount);
471 sc->et.et_name = "ARM MPCore Eventtimer";
472 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
473 sc->et.et_quality = 1000;
475 sc->et.et_frequency = sc->clkfreq;
476 sc->et.et_min_period = (0x00000010LLU << 32) / sc->et.et_frequency;
477 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
478 sc->et.et_start = arm_tmr_start;
479 sc->et.et_stop = arm_tmr_stop;
481 et_register(&sc->et);
484 arm_set_delay(arm_tmr_do_delay, sc);
491 static device_method_t arm_tmr_fdt_methods[] = {
492 DEVMETHOD(device_probe, arm_tmr_fdt_probe),
493 DEVMETHOD(device_attach, arm_tmr_attach),
497 static driver_t arm_tmr_fdt_driver = {
500 sizeof(struct arm_tmr_softc),
503 static devclass_t arm_tmr_fdt_devclass;
505 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
506 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
507 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
508 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
512 static device_method_t arm_tmr_acpi_methods[] = {
513 DEVMETHOD(device_identify, arm_tmr_acpi_identify),
514 DEVMETHOD(device_probe, arm_tmr_acpi_probe),
515 DEVMETHOD(device_attach, arm_tmr_attach),
519 static driver_t arm_tmr_acpi_driver = {
521 arm_tmr_acpi_methods,
522 sizeof(struct arm_tmr_softc),
525 static devclass_t arm_tmr_acpi_devclass;
527 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass,
528 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
532 arm_tmr_do_delay(int usec, void *arg)
534 struct arm_tmr_softc *sc = arg;
535 int32_t counts, counts_per_usec;
536 uint32_t first, last;
538 /* Get the number of times to count */
539 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
542 * Clamp the timeout at a maximum value (about 32 seconds with
543 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
544 * near that length of time and if they are, they should be hung
547 if (usec >= (0x80000000U / counts_per_usec))
548 counts = (0x80000000U / counts_per_usec) - 1;
550 counts = usec * counts_per_usec;
552 first = sc->get_cntxct(sc->physical);
555 last = sc->get_cntxct(sc->physical);
556 counts -= (int32_t)(last - first);
561 #if defined(__aarch64__)
569 * Check the timers are setup, if not just
570 * use a for loop for the meantime
572 if (arm_tmr_sc == NULL) {
573 for (; usec > 0; usec--)
574 for (counts = 200; counts > 0; counts--)
576 * Prevent the compiler from optimizing
581 arm_tmr_do_delay(usec, arm_tmr_sc);
587 arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
588 struct timecounter *tc)
591 vdso_th->th_algo = VDSO_TH_ALGO_ARM_GENTIM;
592 vdso_th->th_physical = arm_tmr_sc->physical;
593 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));