2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
38 #include "opt_platform.h"
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/malloc.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
54 #include <sys/watchdog.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
58 #include <machine/md_var.h>
61 #include <dev/fdt/fdt_common.h>
62 #include <dev/ofw/openfirm.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
68 #include <contrib/dev/acpica/include/acpi.h>
69 #include <dev/acpica/acpivar.h>
72 #define GT_CTRL_ENABLE (1 << 0)
73 #define GT_CTRL_INT_MASK (1 << 1)
74 #define GT_CTRL_INT_STAT (1 << 2)
78 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
79 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
80 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
81 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
82 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
83 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
84 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
86 struct arm_tmr_softc {
87 struct resource *res[4];
94 static struct arm_tmr_softc *arm_tmr_sc = NULL;
96 static struct resource_spec timer_spec[] = {
97 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
98 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
99 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* Virt */
100 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
104 static timecounter_get_t arm_tmr_get_timecount;
106 static struct timecounter arm_tmr_timecount = {
107 .tc_name = "ARM MPCore Timecounter",
108 .tc_get_timecount = arm_tmr_get_timecount,
110 .tc_counter_mask = ~0u,
116 #define get_el0(x) cp15_## x ##_get()
117 #define get_el1(x) cp15_## x ##_get()
118 #define set_el0(x, val) cp15_## x ##_set(val)
119 #define set_el1(x, val) cp15_## x ##_set(val)
120 #else /* __aarch64__ */
121 #define get_el0(x) READ_SPECIALREG(x ##_el0)
122 #define get_el1(x) READ_SPECIALREG(x ##_el1)
123 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
124 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
127 static uint32_t arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
128 struct timecounter *tc);
133 return (get_el0(cntfrq));
137 get_cntxct(bool physical)
143 val = get_el0(cntpct);
145 val = get_el0(cntvct);
151 set_ctrl(uint32_t val, bool physical)
155 set_el0(cntp_ctl, val);
157 set_el0(cntv_ctl, val);
164 set_tval(uint32_t val, bool physical)
168 set_el0(cntp_tval, val);
170 set_el0(cntv_tval, val);
177 get_ctrl(bool physical)
182 val = get_el0(cntp_ctl);
184 val = get_el0(cntv_ctl);
190 setup_user_access(void *arg __unused)
194 cntkctl = get_el1(cntkctl);
195 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
197 if (arm_tmr_sc->physical) {
198 cntkctl |= GT_CNTKCTL_PL0PCTEN;
199 cntkctl &= ~GT_CNTKCTL_PL0VCTEN;
201 cntkctl |= GT_CNTKCTL_PL0VCTEN;
202 cntkctl &= ~GT_CNTKCTL_PL0PCTEN;
204 set_el1(cntkctl, cntkctl);
209 tmr_setup_user_access(void *arg __unused)
212 smp_rendezvous(NULL, setup_user_access, NULL, NULL);
214 SYSINIT(tmr_ua, SI_SUB_SMP, SI_ORDER_SECOND, tmr_setup_user_access, NULL);
217 arm_tmr_get_timecount(struct timecounter *tc)
220 return (get_cntxct(arm_tmr_sc->physical));
224 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
226 struct arm_tmr_softc *sc;
229 sc = (struct arm_tmr_softc *)et->et_priv;
232 counts = ((uint32_t)et->et_frequency * first) >> 32;
233 ctrl = get_ctrl(sc->physical);
234 ctrl &= ~GT_CTRL_INT_MASK;
235 ctrl |= GT_CTRL_ENABLE;
236 set_tval(counts, sc->physical);
237 set_ctrl(ctrl, sc->physical);
246 arm_tmr_stop(struct eventtimer *et)
248 struct arm_tmr_softc *sc;
251 sc = (struct arm_tmr_softc *)et->et_priv;
253 ctrl = get_ctrl(sc->physical);
254 ctrl &= GT_CTRL_ENABLE;
255 set_ctrl(ctrl, sc->physical);
261 arm_tmr_intr(void *arg)
263 struct arm_tmr_softc *sc;
266 sc = (struct arm_tmr_softc *)arg;
267 ctrl = get_ctrl(sc->physical);
268 if (ctrl & GT_CTRL_INT_STAT) {
269 ctrl |= GT_CTRL_INT_MASK;
270 set_ctrl(ctrl, sc->physical);
273 if (sc->et.et_active)
274 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
276 return (FILTER_HANDLED);
281 arm_tmr_fdt_probe(device_t dev)
284 if (!ofw_bus_status_okay(dev))
287 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
288 device_set_desc(dev, "ARMv7 Generic Timer");
289 return (BUS_PROBE_DEFAULT);
290 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
291 device_set_desc(dev, "ARMv8 Generic Timer");
292 return (BUS_PROBE_DEFAULT);
301 arm_tmr_acpi_identify(driver_t *driver, device_t parent)
303 ACPI_TABLE_GTDT *gtdt;
307 physaddr = acpi_find_table(ACPI_SIG_GTDT);
311 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT);
313 device_printf(parent, "gic: Unable to map the GTDT\n");
317 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE,
318 "generic_timer", -1);
320 device_printf(parent, "add gic child failed\n");
324 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 0,
325 gtdt->SecureEl1Interrupt, 1);
326 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 1,
327 gtdt->NonSecureEl1Interrupt, 1);
328 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 2,
329 gtdt->VirtualTimerInterrupt, 1);
332 acpi_unmap_table(gtdt);
336 arm_tmr_acpi_probe(device_t dev)
339 device_set_desc(dev, "ARM Generic Timer");
340 return (BUS_PROBE_NOWILDCARD);
346 arm_tmr_attach(device_t dev)
348 struct arm_tmr_softc *sc;
356 sc = device_get_softc(dev);
361 /* Get the base clock frequency */
362 node = ofw_bus_get_node(dev);
364 error = OF_getencprop(node, "clock-frequency", &clock,
371 if (sc->clkfreq == 0) {
372 /* Try to get clock frequency from timer */
373 sc->clkfreq = get_freq();
376 if (sc->clkfreq == 0) {
377 device_printf(dev, "No clock frequency specified\n");
381 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
382 device_printf(dev, "could not allocate resources\n");
388 #else /* __aarch64__ */
389 sc->physical = false;
394 /* Setup secure, non-secure and virtual IRQs handler */
395 for (i = 0; i < 3; i++) {
396 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
397 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
399 device_printf(dev, "Unable to alloc int resource.\n");
404 arm_cpu_fill_vdso_timehands = arm_tmr_fill_vdso_timehands;
406 arm_tmr_timecount.tc_frequency = sc->clkfreq;
407 tc_init(&arm_tmr_timecount);
409 sc->et.et_name = "ARM MPCore Eventtimer";
410 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
411 sc->et.et_quality = 1000;
413 sc->et.et_frequency = sc->clkfreq;
414 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
415 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
416 sc->et.et_start = arm_tmr_start;
417 sc->et.et_stop = arm_tmr_stop;
419 et_register(&sc->et);
425 static device_method_t arm_tmr_fdt_methods[] = {
426 DEVMETHOD(device_probe, arm_tmr_fdt_probe),
427 DEVMETHOD(device_attach, arm_tmr_attach),
431 static driver_t arm_tmr_fdt_driver = {
434 sizeof(struct arm_tmr_softc),
437 static devclass_t arm_tmr_fdt_devclass;
439 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
440 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
441 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
442 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
446 static device_method_t arm_tmr_acpi_methods[] = {
447 DEVMETHOD(device_identify, arm_tmr_acpi_identify),
448 DEVMETHOD(device_probe, arm_tmr_acpi_probe),
449 DEVMETHOD(device_attach, arm_tmr_attach),
453 static driver_t arm_tmr_acpi_driver = {
455 arm_tmr_acpi_methods,
456 sizeof(struct arm_tmr_softc),
459 static devclass_t arm_tmr_acpi_devclass;
461 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass,
462 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
468 int32_t counts, counts_per_usec;
469 uint32_t first, last;
472 * Check the timers are setup, if not just
473 * use a for loop for the meantime
475 if (arm_tmr_sc == NULL) {
476 for (; usec > 0; usec--)
477 for (counts = 200; counts > 0; counts--)
479 * Prevent the compiler from optimizing
486 /* Get the number of times to count */
487 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
490 * Clamp the timeout at a maximum value (about 32 seconds with
491 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
492 * near that length of time and if they are, they should be hung
495 if (usec >= (0x80000000U / counts_per_usec))
496 counts = (0x80000000U / counts_per_usec) - 1;
498 counts = usec * counts_per_usec;
500 first = get_cntxct(arm_tmr_sc->physical);
503 last = get_cntxct(arm_tmr_sc->physical);
504 counts -= (int32_t)(last - first);
510 arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
511 struct timecounter *tc)
514 vdso_th->th_physical = arm_tmr_sc->physical;
515 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
516 return (tc == &arm_tmr_timecount);