2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2011 The FreeBSD Foundation
5 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
8 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the company nor the name of the author may be used to
19 * endorse or promote products derived from this software without specific
20 * prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
40 #include "opt_platform.h"
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/malloc.h>
52 #include <sys/timeet.h>
53 #include <sys/timetc.h>
56 #include <sys/watchdog.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60 #include <machine/md_var.h>
63 #include <machine/machdep.h> /* For arm_set_delay */
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
73 #include <contrib/dev/acpica/include/acpi.h>
74 #include <dev/acpica/acpivar.h>
75 #include "acpi_bus_if.h"
78 #define GT_CTRL_ENABLE (1 << 0)
79 #define GT_CTRL_INT_MASK (1 << 1)
80 #define GT_CTRL_INT_STAT (1 << 2)
84 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
85 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
86 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
87 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
88 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
89 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
90 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
92 struct arm_tmr_softc {
93 struct resource *res[4];
100 static struct arm_tmr_softc *arm_tmr_sc = NULL;
102 static struct resource_spec timer_spec[] = {
103 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
104 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
105 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, /* Virt */
106 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
110 static uint32_t arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
111 struct timecounter *tc);
112 static void arm_tmr_do_delay(int usec, void *);
114 static timecounter_get_t arm_tmr_get_timecount;
116 static struct timecounter arm_tmr_timecount = {
117 .tc_name = "ARM MPCore Timecounter",
118 .tc_get_timecount = arm_tmr_get_timecount,
120 .tc_counter_mask = ~0u,
123 .tc_fill_vdso_timehands = arm_tmr_fill_vdso_timehands,
127 #define get_el0(x) cp15_## x ##_get()
128 #define get_el1(x) cp15_## x ##_get()
129 #define set_el0(x, val) cp15_## x ##_set(val)
130 #define set_el1(x, val) cp15_## x ##_set(val)
131 #else /* __aarch64__ */
132 #define get_el0(x) READ_SPECIALREG(x ##_el0)
133 #define get_el1(x) READ_SPECIALREG(x ##_el1)
134 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
135 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
141 return (get_el0(cntfrq));
145 get_cntxct(bool physical)
151 val = get_el0(cntpct);
153 val = get_el0(cntvct);
159 set_ctrl(uint32_t val, bool physical)
163 set_el0(cntp_ctl, val);
165 set_el0(cntv_ctl, val);
172 set_tval(uint32_t val, bool physical)
176 set_el0(cntp_tval, val);
178 set_el0(cntv_tval, val);
185 get_ctrl(bool physical)
190 val = get_el0(cntp_ctl);
192 val = get_el0(cntv_ctl);
198 setup_user_access(void *arg __unused)
202 cntkctl = get_el1(cntkctl);
203 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
205 if (arm_tmr_sc->physical) {
206 cntkctl |= GT_CNTKCTL_PL0PCTEN;
207 cntkctl &= ~GT_CNTKCTL_PL0VCTEN;
209 cntkctl |= GT_CNTKCTL_PL0VCTEN;
210 cntkctl &= ~GT_CNTKCTL_PL0PCTEN;
212 set_el1(cntkctl, cntkctl);
217 tmr_setup_user_access(void *arg __unused)
220 if (arm_tmr_sc != NULL)
221 smp_rendezvous(NULL, setup_user_access, NULL, NULL);
223 SYSINIT(tmr_ua, SI_SUB_SMP, SI_ORDER_SECOND, tmr_setup_user_access, NULL);
226 arm_tmr_get_timecount(struct timecounter *tc)
229 return (get_cntxct(arm_tmr_sc->physical));
233 arm_tmr_start(struct eventtimer *et, sbintime_t first,
234 sbintime_t period __unused)
236 struct arm_tmr_softc *sc;
239 sc = (struct arm_tmr_softc *)et->et_priv;
242 counts = ((uint32_t)et->et_frequency * first) >> 32;
243 ctrl = get_ctrl(sc->physical);
244 ctrl &= ~GT_CTRL_INT_MASK;
245 ctrl |= GT_CTRL_ENABLE;
246 set_tval(counts, sc->physical);
247 set_ctrl(ctrl, sc->physical);
256 arm_tmr_disable(bool physical)
260 ctrl = get_ctrl(physical);
261 ctrl &= ~GT_CTRL_ENABLE;
262 set_ctrl(ctrl, physical);
266 arm_tmr_stop(struct eventtimer *et)
268 struct arm_tmr_softc *sc;
270 sc = (struct arm_tmr_softc *)et->et_priv;
271 arm_tmr_disable(sc->physical);
277 arm_tmr_intr(void *arg)
279 struct arm_tmr_softc *sc;
282 sc = (struct arm_tmr_softc *)arg;
283 ctrl = get_ctrl(sc->physical);
284 if (ctrl & GT_CTRL_INT_STAT) {
285 ctrl |= GT_CTRL_INT_MASK;
286 set_ctrl(ctrl, sc->physical);
289 if (sc->et.et_active)
290 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
292 return (FILTER_HANDLED);
297 arm_tmr_fdt_probe(device_t dev)
300 if (!ofw_bus_status_okay(dev))
303 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
304 device_set_desc(dev, "ARMv7 Generic Timer");
305 return (BUS_PROBE_DEFAULT);
306 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
307 device_set_desc(dev, "ARMv8 Generic Timer");
308 return (BUS_PROBE_DEFAULT);
317 arm_tmr_acpi_add_irq(device_t parent, device_t dev, int rid, u_int irq)
320 irq = ACPI_BUS_MAP_INTR(parent, dev, irq,
321 INTR_TRIGGER_LEVEL, INTR_POLARITY_HIGH);
322 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, rid, irq, 1);
326 arm_tmr_acpi_identify(driver_t *driver, device_t parent)
328 ACPI_TABLE_GTDT *gtdt;
332 physaddr = acpi_find_table(ACPI_SIG_GTDT);
336 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT);
338 device_printf(parent, "gic: Unable to map the GTDT\n");
342 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE,
343 "generic_timer", -1);
345 device_printf(parent, "add gic child failed\n");
349 arm_tmr_acpi_add_irq(parent, dev, 0, gtdt->SecureEl1Interrupt);
350 arm_tmr_acpi_add_irq(parent, dev, 1, gtdt->NonSecureEl1Interrupt);
351 arm_tmr_acpi_add_irq(parent, dev, 2, gtdt->VirtualTimerInterrupt);
354 acpi_unmap_table(gtdt);
358 arm_tmr_acpi_probe(device_t dev)
361 device_set_desc(dev, "ARM Generic Timer");
362 return (BUS_PROBE_NOWILDCARD);
368 arm_tmr_attach(device_t dev)
370 struct arm_tmr_softc *sc;
378 sc = device_get_softc(dev);
383 /* Get the base clock frequency */
384 node = ofw_bus_get_node(dev);
386 error = OF_getencprop(node, "clock-frequency", &clock,
393 if (sc->clkfreq == 0) {
394 /* Try to get clock frequency from timer */
395 sc->clkfreq = get_freq();
398 if (sc->clkfreq == 0) {
399 device_printf(dev, "No clock frequency specified\n");
403 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
404 device_printf(dev, "could not allocate resources\n");
410 #else /* __aarch64__ */
411 /* If we do not have a virtual timer use the physical. */
412 sc->physical = (sc->res[2] == NULL) ? true : false;
417 /* Setup secure, non-secure and virtual IRQs handler */
418 for (i = 0; i < 3; i++) {
419 /* If we do not have the interrupt, skip it. */
420 if (sc->res[i] == NULL)
422 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
423 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
425 device_printf(dev, "Unable to alloc int resource.\n");
430 /* Disable the virtual timer until we are ready */
431 if (sc->res[2] != NULL)
432 arm_tmr_disable(false);
433 /* And the physical */
435 arm_tmr_disable(true);
437 arm_tmr_timecount.tc_frequency = sc->clkfreq;
438 tc_init(&arm_tmr_timecount);
440 sc->et.et_name = "ARM MPCore Eventtimer";
441 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
442 sc->et.et_quality = 1000;
444 sc->et.et_frequency = sc->clkfreq;
445 sc->et.et_min_period = (0x00000010LLU << 32) / sc->et.et_frequency;
446 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
447 sc->et.et_start = arm_tmr_start;
448 sc->et.et_stop = arm_tmr_stop;
450 et_register(&sc->et);
453 arm_set_delay(arm_tmr_do_delay, sc);
460 static device_method_t arm_tmr_fdt_methods[] = {
461 DEVMETHOD(device_probe, arm_tmr_fdt_probe),
462 DEVMETHOD(device_attach, arm_tmr_attach),
466 static driver_t arm_tmr_fdt_driver = {
469 sizeof(struct arm_tmr_softc),
472 static devclass_t arm_tmr_fdt_devclass;
474 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
475 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
476 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
477 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
481 static device_method_t arm_tmr_acpi_methods[] = {
482 DEVMETHOD(device_identify, arm_tmr_acpi_identify),
483 DEVMETHOD(device_probe, arm_tmr_acpi_probe),
484 DEVMETHOD(device_attach, arm_tmr_attach),
488 static driver_t arm_tmr_acpi_driver = {
490 arm_tmr_acpi_methods,
491 sizeof(struct arm_tmr_softc),
494 static devclass_t arm_tmr_acpi_devclass;
496 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass,
497 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
501 arm_tmr_do_delay(int usec, void *arg)
503 struct arm_tmr_softc *sc = arg;
504 int32_t counts, counts_per_usec;
505 uint32_t first, last;
507 /* Get the number of times to count */
508 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
511 * Clamp the timeout at a maximum value (about 32 seconds with
512 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
513 * near that length of time and if they are, they should be hung
516 if (usec >= (0x80000000U / counts_per_usec))
517 counts = (0x80000000U / counts_per_usec) - 1;
519 counts = usec * counts_per_usec;
521 first = get_cntxct(sc->physical);
524 last = get_cntxct(sc->physical);
525 counts -= (int32_t)(last - first);
530 #if defined(__aarch64__)
538 * Check the timers are setup, if not just
539 * use a for loop for the meantime
541 if (arm_tmr_sc == NULL) {
542 for (; usec > 0; usec--)
543 for (counts = 200; counts > 0; counts--)
545 * Prevent the compiler from optimizing
550 arm_tmr_do_delay(usec, arm_tmr_sc);
556 arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
557 struct timecounter *tc)
560 vdso_th->th_algo = VDSO_TH_ALGO_ARM_GENTIM;
561 vdso_th->th_physical = arm_tmr_sc->physical;
562 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));