2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
38 #include "opt_platform.h"
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/malloc.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
54 #include <sys/watchdog.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
58 #include <machine/md_var.h>
61 #include <machine/machdep.h> /* For arm_set_delay */
65 #include <dev/fdt/fdt_common.h>
66 #include <dev/ofw/openfirm.h>
67 #include <dev/ofw/ofw_bus.h>
68 #include <dev/ofw/ofw_bus_subr.h>
72 #include <contrib/dev/acpica/include/acpi.h>
73 #include <dev/acpica/acpivar.h>
76 #define GT_CTRL_ENABLE (1 << 0)
77 #define GT_CTRL_INT_MASK (1 << 1)
78 #define GT_CTRL_INT_STAT (1 << 2)
82 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
83 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
84 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
85 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
86 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
87 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
88 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
90 struct arm_tmr_softc {
91 struct resource *res[4];
98 static struct arm_tmr_softc *arm_tmr_sc = NULL;
100 static struct resource_spec timer_spec[] = {
101 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
102 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
103 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, /* Virt */
104 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
108 static uint32_t arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
109 struct timecounter *tc);
110 static void arm_tmr_do_delay(int usec, void *);
112 static timecounter_get_t arm_tmr_get_timecount;
114 static struct timecounter arm_tmr_timecount = {
115 .tc_name = "ARM MPCore Timecounter",
116 .tc_get_timecount = arm_tmr_get_timecount,
118 .tc_counter_mask = ~0u,
121 .tc_fill_vdso_timehands = arm_tmr_fill_vdso_timehands,
125 #define get_el0(x) cp15_## x ##_get()
126 #define get_el1(x) cp15_## x ##_get()
127 #define set_el0(x, val) cp15_## x ##_set(val)
128 #define set_el1(x, val) cp15_## x ##_set(val)
129 #else /* __aarch64__ */
130 #define get_el0(x) READ_SPECIALREG(x ##_el0)
131 #define get_el1(x) READ_SPECIALREG(x ##_el1)
132 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
133 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
139 return (get_el0(cntfrq));
143 get_cntxct(bool physical)
149 val = get_el0(cntpct);
151 val = get_el0(cntvct);
157 set_ctrl(uint32_t val, bool physical)
161 set_el0(cntp_ctl, val);
163 set_el0(cntv_ctl, val);
170 set_tval(uint32_t val, bool physical)
174 set_el0(cntp_tval, val);
176 set_el0(cntv_tval, val);
183 get_ctrl(bool physical)
188 val = get_el0(cntp_ctl);
190 val = get_el0(cntv_ctl);
196 setup_user_access(void *arg __unused)
200 cntkctl = get_el1(cntkctl);
201 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
203 if (arm_tmr_sc->physical) {
204 cntkctl |= GT_CNTKCTL_PL0PCTEN;
205 cntkctl &= ~GT_CNTKCTL_PL0VCTEN;
207 cntkctl |= GT_CNTKCTL_PL0VCTEN;
208 cntkctl &= ~GT_CNTKCTL_PL0PCTEN;
210 set_el1(cntkctl, cntkctl);
215 tmr_setup_user_access(void *arg __unused)
218 if (arm_tmr_sc != NULL)
219 smp_rendezvous(NULL, setup_user_access, NULL, NULL);
221 SYSINIT(tmr_ua, SI_SUB_SMP, SI_ORDER_SECOND, tmr_setup_user_access, NULL);
224 arm_tmr_get_timecount(struct timecounter *tc)
227 return (get_cntxct(arm_tmr_sc->physical));
231 arm_tmr_start(struct eventtimer *et, sbintime_t first,
232 sbintime_t period __unused)
234 struct arm_tmr_softc *sc;
237 sc = (struct arm_tmr_softc *)et->et_priv;
240 counts = ((uint32_t)et->et_frequency * first) >> 32;
241 ctrl = get_ctrl(sc->physical);
242 ctrl &= ~GT_CTRL_INT_MASK;
243 ctrl |= GT_CTRL_ENABLE;
244 set_tval(counts, sc->physical);
245 set_ctrl(ctrl, sc->physical);
254 arm_tmr_stop(struct eventtimer *et)
256 struct arm_tmr_softc *sc;
259 sc = (struct arm_tmr_softc *)et->et_priv;
261 ctrl = get_ctrl(sc->physical);
262 ctrl &= GT_CTRL_ENABLE;
263 set_ctrl(ctrl, sc->physical);
269 arm_tmr_intr(void *arg)
271 struct arm_tmr_softc *sc;
274 sc = (struct arm_tmr_softc *)arg;
275 ctrl = get_ctrl(sc->physical);
276 if (ctrl & GT_CTRL_INT_STAT) {
277 ctrl |= GT_CTRL_INT_MASK;
278 set_ctrl(ctrl, sc->physical);
281 if (sc->et.et_active)
282 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
284 return (FILTER_HANDLED);
289 arm_tmr_fdt_probe(device_t dev)
292 if (!ofw_bus_status_okay(dev))
295 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
296 device_set_desc(dev, "ARMv7 Generic Timer");
297 return (BUS_PROBE_DEFAULT);
298 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
299 device_set_desc(dev, "ARMv8 Generic Timer");
300 return (BUS_PROBE_DEFAULT);
309 arm_tmr_acpi_identify(driver_t *driver, device_t parent)
311 ACPI_TABLE_GTDT *gtdt;
315 physaddr = acpi_find_table(ACPI_SIG_GTDT);
319 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT);
321 device_printf(parent, "gic: Unable to map the GTDT\n");
325 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE,
326 "generic_timer", -1);
328 device_printf(parent, "add gic child failed\n");
332 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 0,
333 gtdt->SecureEl1Interrupt, 1);
334 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 1,
335 gtdt->NonSecureEl1Interrupt, 1);
336 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 2,
337 gtdt->VirtualTimerInterrupt, 1);
340 acpi_unmap_table(gtdt);
344 arm_tmr_acpi_probe(device_t dev)
347 device_set_desc(dev, "ARM Generic Timer");
348 return (BUS_PROBE_NOWILDCARD);
354 arm_tmr_attach(device_t dev)
356 struct arm_tmr_softc *sc;
364 sc = device_get_softc(dev);
369 /* Get the base clock frequency */
370 node = ofw_bus_get_node(dev);
372 error = OF_getencprop(node, "clock-frequency", &clock,
379 if (sc->clkfreq == 0) {
380 /* Try to get clock frequency from timer */
381 sc->clkfreq = get_freq();
384 if (sc->clkfreq == 0) {
385 device_printf(dev, "No clock frequency specified\n");
389 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
390 device_printf(dev, "could not allocate resources\n");
396 #else /* __aarch64__ */
397 /* If we do not have a virtual timer use the physical. */
398 sc->physical = (sc->res[2] == NULL) ? true : false;
403 /* Setup secure, non-secure and virtual IRQs handler */
404 for (i = 0; i < 3; i++) {
405 /* If we do not have the interrupt, skip it. */
406 if (sc->res[i] == NULL)
408 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
409 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
411 device_printf(dev, "Unable to alloc int resource.\n");
416 arm_tmr_timecount.tc_frequency = sc->clkfreq;
417 tc_init(&arm_tmr_timecount);
419 sc->et.et_name = "ARM MPCore Eventtimer";
420 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
421 sc->et.et_quality = 1000;
423 sc->et.et_frequency = sc->clkfreq;
424 sc->et.et_min_period = (0x00000010LLU << 32) / sc->et.et_frequency;
425 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
426 sc->et.et_start = arm_tmr_start;
427 sc->et.et_stop = arm_tmr_stop;
429 et_register(&sc->et);
432 arm_set_delay(arm_tmr_do_delay, sc);
439 static device_method_t arm_tmr_fdt_methods[] = {
440 DEVMETHOD(device_probe, arm_tmr_fdt_probe),
441 DEVMETHOD(device_attach, arm_tmr_attach),
445 static driver_t arm_tmr_fdt_driver = {
448 sizeof(struct arm_tmr_softc),
451 static devclass_t arm_tmr_fdt_devclass;
453 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
454 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
455 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass,
456 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
460 static device_method_t arm_tmr_acpi_methods[] = {
461 DEVMETHOD(device_identify, arm_tmr_acpi_identify),
462 DEVMETHOD(device_probe, arm_tmr_acpi_probe),
463 DEVMETHOD(device_attach, arm_tmr_attach),
467 static driver_t arm_tmr_acpi_driver = {
469 arm_tmr_acpi_methods,
470 sizeof(struct arm_tmr_softc),
473 static devclass_t arm_tmr_acpi_devclass;
475 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass,
476 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
480 arm_tmr_do_delay(int usec, void *arg)
482 struct arm_tmr_softc *sc = arg;
483 int32_t counts, counts_per_usec;
484 uint32_t first, last;
486 /* Get the number of times to count */
487 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
490 * Clamp the timeout at a maximum value (about 32 seconds with
491 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
492 * near that length of time and if they are, they should be hung
495 if (usec >= (0x80000000U / counts_per_usec))
496 counts = (0x80000000U / counts_per_usec) - 1;
498 counts = usec * counts_per_usec;
500 first = get_cntxct(sc->physical);
503 last = get_cntxct(sc->physical);
504 counts -= (int32_t)(last - first);
516 * Check the timers are setup, if not just
517 * use a for loop for the meantime
519 if (arm_tmr_sc == NULL) {
520 for (; usec > 0; usec--)
521 for (counts = 200; counts > 0; counts--)
523 * Prevent the compiler from optimizing
528 arm_tmr_do_delay(usec, arm_tmr_sc);
533 arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th,
534 struct timecounter *tc)
537 vdso_th->th_algo = VDSO_TH_ALGO_ARM_GENTIM;
538 vdso_th->th_physical = arm_tmr_sc->physical;
539 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));