2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A15 (and probably A7) Generic Timer
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
47 #include <sys/timeet.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
50 #include <machine/bus.h>
51 #include <machine/cpu.h>
52 #include <machine/intr.h>
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <machine/bus.h>
60 #include <machine/fdt.h>
62 #define GT_CTRL_ENABLE (1 << 0)
63 #define GT_CTRL_INT_MASK (1 << 1)
64 #define GT_CTRL_INT_STAT (1 << 2)
68 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
69 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
70 #define GT_CNTKCTL_EVNTI (1 << 4) /* Virtual counter event bits */
71 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
72 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
73 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
74 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
76 #define GT_CNTPSIRQ 29
78 struct arm_tmr_softc {
79 struct resource *irq_res;
84 static struct arm_tmr_softc *arm_tmr_sc = NULL;
86 static timecounter_get_t arm_tmr_get_timecount;
88 static struct timecounter arm_tmr_timecount = {
89 .tc_name = "ARM MPCore Timecounter",
90 .tc_get_timecount = arm_tmr_get_timecount,
92 .tc_counter_mask = ~0u,
102 __asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
108 set_freq(uint32_t val)
111 __asm volatile("mcr p15, 0, %[val], c14, c0, 0" : :
124 __asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
130 set_ctrl(uint32_t val)
133 __asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
141 set_tval(uint32_t val)
144 __asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
156 __asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
166 __asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
172 disable_user_access(void)
176 __asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
177 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
178 GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
179 __asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
184 arm_tmr_get_timecount(struct timecounter *tc)
187 return (get_cntpct());
191 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
193 struct arm_tmr_softc *sc;
196 sc = (struct arm_tmr_softc *)et->et_priv;
199 counts = ((uint32_t)et->et_frequency * first) >> 32;
201 ctrl &= ~GT_CTRL_INT_MASK;
202 ctrl |= GT_CTRL_ENABLE;
213 arm_tmr_stop(struct eventtimer *et)
218 ctrl &= GT_CTRL_ENABLE;
225 arm_tmr_intr(void *arg)
227 struct arm_tmr_softc *sc;
230 sc = (struct arm_tmr_softc *)arg;
232 if (ctrl & GT_CTRL_INT_STAT) {
233 ctrl |= GT_CTRL_INT_MASK;
237 if (sc->et.et_active)
238 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
240 return (FILTER_HANDLED);
244 arm_tmr_probe(device_t dev)
247 if (!ofw_bus_status_okay(dev))
250 if (!ofw_bus_is_compatible(dev, "arm,armv7-timer"))
253 device_set_desc(dev, "ARMv7 Generic Timer");
254 return (BUS_PROBE_DEFAULT);
259 arm_tmr_attach(device_t dev)
261 struct arm_tmr_softc *sc;
268 sc = device_get_softc(dev);
272 /* Get the base clock frequency */
273 node = ofw_bus_get_node(dev);
274 error = OF_getprop(node, "clock-frequency", &clock, sizeof(clock));
276 device_printf(dev, "missing clock-frequency "
277 "attribute in FDT\n");
280 sc->clkfreq = fdt32_to_cpu(clock);
283 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
284 GT_CNTPSIRQ, GT_CNTPSIRQ,
285 1, RF_SHAREABLE | RF_ACTIVE);
289 /* Setup and enable the timer */
290 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, arm_tmr_intr,
291 NULL, sc, &ihl) != 0) {
292 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->irq_res);
293 device_printf(dev, "Unable to setup the CLK irq handler.\n");
297 set_freq(sc->clkfreq);
298 disable_user_access();
300 arm_tmr_timecount.tc_frequency = sc->clkfreq;
301 tc_init(&arm_tmr_timecount);
303 sc->et.et_name = "ARM MPCore Eventtimer";
304 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
305 sc->et.et_quality = 1000;
307 sc->et.et_frequency = sc->clkfreq;
308 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
309 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
310 sc->et.et_start = arm_tmr_start;
311 sc->et.et_stop = arm_tmr_stop;
313 et_register(&sc->et);
318 static device_method_t arm_tmr_methods[] = {
319 DEVMETHOD(device_probe, arm_tmr_probe),
320 DEVMETHOD(device_attach, arm_tmr_attach),
324 static driver_t arm_tmr_driver = {
327 sizeof(struct arm_tmr_softc),
330 static devclass_t arm_tmr_devclass;
332 DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
338 if (PCPU_GET(cpuid) == 0)
339 cpu_initclocks_bsp();
347 int32_t counts, counts_per_usec;
348 uint32_t first, last;
351 * Check the timers are setup, if not just
352 * use a for loop for the meantime
354 if (arm_tmr_sc == NULL) {
355 for (; usec > 0; usec--)
356 for (counts = 200; counts > 0; counts--)
358 * Prevent gcc from optimizing
365 /* Get the number of times to count */
366 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
369 * Clamp the timeout at a maximum value (about 32 seconds with
370 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
371 * near that length of time and if they are, they should be hung
374 if (usec >= (0x80000000U / counts_per_usec))
375 counts = (0x80000000U / counts_per_usec) - 1;
377 counts = usec * counts_per_usec;
379 first = get_cntpct();
383 counts -= (int32_t)(last - first);