2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A15 (and probably A7) Generic Timer
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
47 #include <sys/timeet.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
50 #include <machine/bus.h>
51 #include <machine/cpu.h>
52 #include <machine/intr.h>
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <machine/bus.h>
60 #include <machine/fdt.h>
62 #define GT_CTRL_ENABLE (1 << 0)
63 #define GT_CTRL_INT_MASK (1 << 1)
64 #define GT_CTRL_INT_STAT (1 << 2)
68 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
69 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
70 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
71 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
72 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
73 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
74 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
76 struct arm_tmr_softc {
77 struct resource *res[4];
84 static struct arm_tmr_softc *arm_tmr_sc = NULL;
86 static struct resource_spec timer_spec[] = {
87 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
88 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
89 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* Virt */
90 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
94 static timecounter_get_t arm_tmr_get_timecount;
96 static struct timecounter arm_tmr_timecount = {
97 .tc_name = "ARM MPCore Timecounter",
98 .tc_get_timecount = arm_tmr_get_timecount,
100 .tc_counter_mask = ~0u,
111 __asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
117 get_cntxct(bool physical)
124 __asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
127 __asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (val));
133 set_ctrl(uint32_t val, bool physical)
138 __asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
142 __asm volatile("mcr p15, 0, %[val], c14, c3, 1" : :
150 set_tval(uint32_t val, bool physical)
155 __asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
159 __asm volatile("mcr p15, 0, %[val], c14, c3, 0" : :
167 get_ctrl(bool physical)
173 __asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
176 __asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
182 disable_user_access(void)
186 __asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
187 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
188 GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
189 __asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
194 arm_tmr_get_timecount(struct timecounter *tc)
197 return (get_cntxct(arm_tmr_sc->physical));
201 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
203 struct arm_tmr_softc *sc;
206 sc = (struct arm_tmr_softc *)et->et_priv;
209 counts = ((uint32_t)et->et_frequency * first) >> 32;
210 ctrl = get_ctrl(sc->physical);
211 ctrl &= ~GT_CTRL_INT_MASK;
212 ctrl |= GT_CTRL_ENABLE;
213 set_tval(counts, sc->physical);
214 set_ctrl(ctrl, sc->physical);
223 arm_tmr_stop(struct eventtimer *et)
225 struct arm_tmr_softc *sc;
228 sc = (struct arm_tmr_softc *)et->et_priv;
230 ctrl = get_ctrl(sc->physical);
231 ctrl &= GT_CTRL_ENABLE;
232 set_ctrl(ctrl, sc->physical);
238 arm_tmr_intr(void *arg)
240 struct arm_tmr_softc *sc;
243 sc = (struct arm_tmr_softc *)arg;
244 ctrl = get_ctrl(sc->physical);
245 if (ctrl & GT_CTRL_INT_STAT) {
246 ctrl |= GT_CTRL_INT_MASK;
247 set_ctrl(ctrl, sc->physical);
250 if (sc->et.et_active)
251 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
253 return (FILTER_HANDLED);
257 arm_tmr_probe(device_t dev)
260 if (!ofw_bus_status_okay(dev))
263 if (!ofw_bus_is_compatible(dev, "arm,armv7-timer"))
266 device_set_desc(dev, "ARMv7 Generic Timer");
267 return (BUS_PROBE_DEFAULT);
272 arm_tmr_attach(device_t dev)
274 struct arm_tmr_softc *sc;
280 sc = device_get_softc(dev);
284 /* Get the base clock frequency */
285 node = ofw_bus_get_node(dev);
286 error = OF_getprop(node, "clock-frequency", &clock, sizeof(clock));
288 sc->clkfreq = fdt32_to_cpu(clock);
291 if (sc->clkfreq == 0) {
292 /* Try to get clock frequency from timer */
293 sc->clkfreq = get_freq();
296 if (sc->clkfreq == 0) {
297 device_printf(dev, "No clock frequency specified\n");
301 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
302 device_printf(dev, "could not allocate resources\n");
310 /* Setup secure, non-secure and virtual IRQs handler */
311 for (i = 0; i < 3; i++) {
312 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
313 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
315 device_printf(dev, "Unable to alloc int resource.\n");
320 disable_user_access();
322 arm_tmr_timecount.tc_frequency = sc->clkfreq;
323 tc_init(&arm_tmr_timecount);
325 sc->et.et_name = "ARM MPCore Eventtimer";
326 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
327 sc->et.et_quality = 1000;
329 sc->et.et_frequency = sc->clkfreq;
330 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
331 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
332 sc->et.et_start = arm_tmr_start;
333 sc->et.et_stop = arm_tmr_stop;
335 et_register(&sc->et);
340 static device_method_t arm_tmr_methods[] = {
341 DEVMETHOD(device_probe, arm_tmr_probe),
342 DEVMETHOD(device_attach, arm_tmr_attach),
346 static driver_t arm_tmr_driver = {
349 sizeof(struct arm_tmr_softc),
352 static devclass_t arm_tmr_devclass;
354 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
355 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
356 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
357 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
362 int32_t counts, counts_per_usec;
363 uint32_t first, last;
366 * Check the timers are setup, if not just
367 * use a for loop for the meantime
369 if (arm_tmr_sc == NULL) {
370 for (; usec > 0; usec--)
371 for (counts = 200; counts > 0; counts--)
373 * Prevent gcc from optimizing
380 /* Get the number of times to count */
381 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
384 * Clamp the timeout at a maximum value (about 32 seconds with
385 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
386 * near that length of time and if they are, they should be hung
389 if (usec >= (0x80000000U / counts_per_usec))
390 counts = (0x80000000U / counts_per_usec) - 1;
392 counts = usec * counts_per_usec;
394 first = get_cntxct(arm_tmr_sc->physical);
397 last = get_cntxct(arm_tmr_sc->physical);
398 counts -= (int32_t)(last - first);