2 * Copyright (c) 2011 The FreeBSD Foundation
3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the name of the author may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
47 #include <sys/timeet.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
50 #include <machine/bus.h>
51 #include <machine/cpu.h>
52 #include <machine/intr.h>
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <machine/bus.h>
61 #define GT_CTRL_ENABLE (1 << 0)
62 #define GT_CTRL_INT_MASK (1 << 1)
63 #define GT_CTRL_INT_STAT (1 << 2)
67 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
68 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
69 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */
70 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */
71 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */
72 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
73 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
75 struct arm_tmr_softc {
76 struct resource *res[4];
83 static struct arm_tmr_softc *arm_tmr_sc = NULL;
85 static struct resource_spec timer_spec[] = {
86 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */
87 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */
88 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* Virt */
89 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */
93 static timecounter_get_t arm_tmr_get_timecount;
95 static struct timecounter arm_tmr_timecount = {
96 .tc_name = "ARM MPCore Timecounter",
97 .tc_get_timecount = arm_tmr_get_timecount,
99 .tc_counter_mask = ~0u,
105 #define get_el0(x) cp15_## x ##_get()
106 #define get_el1(x) cp15_## x ##_get()
107 #define set_el0(x, val) cp15_## x ##_set(val)
108 #define set_el1(x, val) cp15_## x ##_set(val)
109 #else /* __aarch64__ */
110 #define get_el0(x) READ_SPECIALREG(x ##_el0)
111 #define get_el1(x) READ_SPECIALREG(x ##_el1)
112 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val)
113 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val)
119 return (get_el0(cntfrq));
123 get_cntxct(bool physical)
129 val = get_el0(cntpct);
131 val = get_el0(cntvct);
137 set_ctrl(uint32_t val, bool physical)
141 set_el0(cntp_ctl, val);
143 set_el0(cntv_ctl, val);
150 set_tval(uint32_t val, bool physical)
154 set_el0(cntp_tval, val);
156 set_el0(cntv_tval, val);
163 get_ctrl(bool physical)
168 val = get_el0(cntp_ctl);
170 val = get_el0(cntv_ctl);
176 disable_user_access(void)
180 cntkctl = get_el1(cntkctl);
181 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
182 GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
183 set_el1(cntkctl, cntkctl);
188 arm_tmr_get_timecount(struct timecounter *tc)
191 return (get_cntxct(arm_tmr_sc->physical));
195 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
197 struct arm_tmr_softc *sc;
200 sc = (struct arm_tmr_softc *)et->et_priv;
203 counts = ((uint32_t)et->et_frequency * first) >> 32;
204 ctrl = get_ctrl(sc->physical);
205 ctrl &= ~GT_CTRL_INT_MASK;
206 ctrl |= GT_CTRL_ENABLE;
207 set_tval(counts, sc->physical);
208 set_ctrl(ctrl, sc->physical);
217 arm_tmr_stop(struct eventtimer *et)
219 struct arm_tmr_softc *sc;
222 sc = (struct arm_tmr_softc *)et->et_priv;
224 ctrl = get_ctrl(sc->physical);
225 ctrl &= GT_CTRL_ENABLE;
226 set_ctrl(ctrl, sc->physical);
232 arm_tmr_intr(void *arg)
234 struct arm_tmr_softc *sc;
237 sc = (struct arm_tmr_softc *)arg;
238 ctrl = get_ctrl(sc->physical);
239 if (ctrl & GT_CTRL_INT_STAT) {
240 ctrl |= GT_CTRL_INT_MASK;
241 set_ctrl(ctrl, sc->physical);
244 if (sc->et.et_active)
245 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
247 return (FILTER_HANDLED);
251 arm_tmr_probe(device_t dev)
254 if (!ofw_bus_status_okay(dev))
257 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) {
258 device_set_desc(dev, "ARMv7 Generic Timer");
259 return (BUS_PROBE_DEFAULT);
260 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) {
261 device_set_desc(dev, "ARMv8 Generic Timer");
262 return (BUS_PROBE_DEFAULT);
270 arm_tmr_attach(device_t dev)
272 struct arm_tmr_softc *sc;
278 sc = device_get_softc(dev);
282 /* Get the base clock frequency */
283 node = ofw_bus_get_node(dev);
284 error = OF_getprop(node, "clock-frequency", &clock, sizeof(clock));
286 sc->clkfreq = fdt32_to_cpu(clock);
289 if (sc->clkfreq == 0) {
290 /* Try to get clock frequency from timer */
291 sc->clkfreq = get_freq();
294 if (sc->clkfreq == 0) {
295 device_printf(dev, "No clock frequency specified\n");
299 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
300 device_printf(dev, "could not allocate resources\n");
306 #else /* __aarch64__ */
307 sc->physical = false;
312 /* Setup secure, non-secure and virtual IRQs handler */
313 for (i = 0; i < 3; i++) {
314 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK,
315 arm_tmr_intr, NULL, sc, &sc->ihl[i]);
317 device_printf(dev, "Unable to alloc int resource.\n");
322 disable_user_access();
324 arm_tmr_timecount.tc_frequency = sc->clkfreq;
325 tc_init(&arm_tmr_timecount);
327 sc->et.et_name = "ARM MPCore Eventtimer";
328 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
329 sc->et.et_quality = 1000;
331 sc->et.et_frequency = sc->clkfreq;
332 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
333 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
334 sc->et.et_start = arm_tmr_start;
335 sc->et.et_stop = arm_tmr_stop;
337 et_register(&sc->et);
342 static device_method_t arm_tmr_methods[] = {
343 DEVMETHOD(device_probe, arm_tmr_probe),
344 DEVMETHOD(device_attach, arm_tmr_attach),
348 static driver_t arm_tmr_driver = {
351 sizeof(struct arm_tmr_softc),
354 static devclass_t arm_tmr_devclass;
356 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
357 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
358 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
359 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
364 int32_t counts, counts_per_usec;
365 uint32_t first, last;
368 * Check the timers are setup, if not just
369 * use a for loop for the meantime
371 if (arm_tmr_sc == NULL) {
372 for (; usec > 0; usec--)
373 for (counts = 200; counts > 0; counts--)
375 * Prevent the compiler from optimizing
382 /* Get the number of times to count */
383 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
386 * Clamp the timeout at a maximum value (about 32 seconds with
387 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
388 * near that length of time and if they are, they should be hung
391 if (usec >= (0x80000000U / counts_per_usec))
392 counts = (0x80000000U / counts_per_usec) - 1;
394 counts = usec * counts_per_usec;
396 first = get_cntxct(arm_tmr_sc->physical);
399 last = get_cntxct(arm_tmr_sc->physical);
400 counts -= (int32_t)(last - first);