2 * Copyright (c) 2011 The FreeBSD Foundation
5 * Developed by Damjan Marion <damjan.marion@gmail.com>
7 * Based on OMAP4 GIC code by Ben Gray
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/module.h>
46 #include <sys/cpuset.h>
48 #include <sys/mutex.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51 #include <machine/smp.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 /* We are using GICv2 register naming */
60 /* Distributor Registers */
61 #define GICD_CTLR 0x000 /* v1 ICDDCR */
62 #define GICD_TYPER 0x004 /* v1 ICDICTR */
63 #define GICD_IIDR 0x008 /* v1 ICDIIDR */
64 #define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
65 #define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
66 #define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
67 #define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
68 #define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
69 #define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
70 #define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
71 #define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
72 #define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
73 #define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
76 #define GICC_CTLR 0x0000 /* v1 ICCICR */
77 #define GICC_PMR 0x0004 /* v1 ICCPMR */
78 #define GICC_BPR 0x0008 /* v1 ICCBPR */
79 #define GICC_IAR 0x000C /* v1 ICCIAR */
80 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
81 #define GICC_RPR 0x0014 /* v1 ICCRPR */
82 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
83 #define GICC_ABPR 0x001C /* v1 ICCABPR */
84 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
86 #define GIC_LAST_IPI 15 /* Irqs 0-15 are IPIs. */
88 /* First bit is a polarity bit (0 - low, 1 - high) */
89 #define GICD_ICFGR_POL_LOW (0 << 0)
90 #define GICD_ICFGR_POL_HIGH (1 << 0)
91 #define GICD_ICFGR_POL_MASK 0x1
92 /* Second bit is a trigger bit (0 - level, 1 - edge) */
93 #define GICD_ICFGR_TRIG_LVL (0 << 1)
94 #define GICD_ICFGR_TRIG_EDGE (1 << 1)
95 #define GICD_ICFGR_TRIG_MASK 0x2
97 struct arm_gic_softc {
98 struct resource * gic_res[3];
99 bus_space_tag_t gic_c_bst;
100 bus_space_tag_t gic_d_bst;
101 bus_space_handle_t gic_c_bsh;
102 bus_space_handle_t gic_d_bsh;
109 static struct resource_spec arm_gic_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
111 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
115 static struct arm_gic_softc *arm_gic_sc = NULL;
117 #define gic_c_read_4(reg) \
118 bus_space_read_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg)
119 #define gic_c_write_4(reg, val) \
120 bus_space_write_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg, val)
121 #define gic_d_read_4(reg) \
122 bus_space_read_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg)
123 #define gic_d_write_4(reg, val) \
124 bus_space_write_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg, val)
126 static int gic_config_irq(int irq, enum intr_trigger trig,
127 enum intr_polarity pol);
128 static void gic_post_filter(void *);
131 arm_gic_probe(device_t dev)
134 if (!ofw_bus_status_okay(dev))
137 if (!ofw_bus_is_compatible(dev, "arm,gic"))
139 device_set_desc(dev, "ARM Generic Interrupt Controller");
140 return (BUS_PROBE_DEFAULT);
144 gic_init_secondary(void)
148 /* Get the number of interrupts */
149 nirqs = gic_d_read_4(GICD_TYPER);
150 nirqs = 32 * ((nirqs & 0x1f) + 1);
152 for (i = 0; i < nirqs; i += 4)
153 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
155 /* Set all the interrupts to be in Group 0 (secure) */
156 for (i = 0; i < nirqs; i += 32) {
157 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
160 /* Enable CPU interface */
161 gic_c_write_4(GICC_CTLR, 1);
163 /* Set priority mask register. */
164 gic_c_write_4(GICC_PMR, 0xff);
166 /* Enable interrupt distribution */
167 gic_d_write_4(GICD_CTLR, 0x01);
170 * Activate the timer interrupts: virtual, secure, and non-secure.
172 gic_d_write_4(GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
173 gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
174 gic_d_write_4(GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
178 arm_gic_attach(device_t dev)
180 struct arm_gic_softc *sc;
187 sc = device_get_softc(dev);
190 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
191 device_printf(dev, "could not allocate resources\n");
195 /* Initialize mutex */
196 mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
198 /* Distributor Interface */
199 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
200 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
203 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
204 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
208 /* Disable interrupt forwarding to the CPU interface */
209 gic_d_write_4(GICD_CTLR, 0x00);
211 /* Get the number of interrupts */
212 sc->nirqs = gic_d_read_4(GICD_TYPER);
213 sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
215 /* Set up function pointers */
216 arm_post_filter = gic_post_filter;
217 arm_config_irq = gic_config_irq;
219 icciidr = gic_c_read_4(GICC_IIDR);
220 device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x sc->nirqs %u\n",
221 icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
222 (icciidr & 0xfff), sc->nirqs);
224 /* Set all global interrupts to be level triggered, active low. */
225 for (i = 32; i < sc->nirqs; i += 16) {
226 gic_d_write_4(GICD_ICFGR(i >> 4), 0x00000000);
229 /* Disable all interrupts. */
230 for (i = 32; i < sc->nirqs; i += 32) {
231 gic_d_write_4(GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
234 for (i = 0; i < sc->nirqs; i += 4) {
235 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
236 gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
239 /* Set all the interrupts to be in Group 0 (secure) */
240 for (i = 0; i < sc->nirqs; i += 32) {
241 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
244 /* Enable CPU interface */
245 gic_c_write_4(GICC_CTLR, 1);
247 /* Set priority mask register. */
248 gic_c_write_4(GICC_PMR, 0xff);
250 /* Enable interrupt distribution */
251 gic_d_write_4(GICD_CTLR, 0x01);
256 static device_method_t arm_gic_methods[] = {
257 DEVMETHOD(device_probe, arm_gic_probe),
258 DEVMETHOD(device_attach, arm_gic_attach),
262 static driver_t arm_gic_driver = {
265 sizeof(struct arm_gic_softc),
268 static devclass_t arm_gic_devclass;
270 EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0,
271 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
274 gic_post_filter(void *arg)
276 uintptr_t irq = (uintptr_t) arg;
278 if (irq > GIC_LAST_IPI)
279 arm_irq_memory_barrier(irq);
280 gic_c_write_4(GICC_EOIR, irq);
284 arm_get_next_irq(int last_irq)
288 active_irq = gic_c_read_4(GICC_IAR);
291 * Immediatly EOIR the SGIs, because doing so requires the other
292 * bits (ie CPU number), not just the IRQ number, and we do not
293 * have this information later.
296 if ((active_irq & 0x3ff) <= GIC_LAST_IPI)
297 gic_c_write_4(GICC_EOIR, active_irq);
300 if (active_irq == 0x3FF) {
302 printf("Spurious interrupt detected\n");
310 arm_mask_irq(uintptr_t nb)
313 gic_d_write_4(GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
314 gic_c_write_4(GICC_EOIR, nb);
318 arm_unmask_irq(uintptr_t nb)
321 if (nb > GIC_LAST_IPI)
322 arm_irq_memory_barrier(nb);
323 gic_d_write_4(GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
327 gic_config_irq(int irq, enum intr_trigger trig,
328 enum intr_polarity pol)
333 /* Function is public-accessible, so validate input arguments */
334 if ((irq < 0) || (irq >= arm_gic_sc->nirqs))
336 if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
337 (trig != INTR_TRIGGER_CONFORM))
339 if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) &&
340 (pol != INTR_POLARITY_CONFORM))
343 mtx_lock_spin(&arm_gic_sc->mutex);
345 reg = gic_d_read_4(GICD_ICFGR(irq >> 4));
346 mask = (reg >> 2*(irq % 16)) & 0x3;
348 if (pol == INTR_POLARITY_LOW) {
349 mask &= ~GICD_ICFGR_POL_MASK;
350 mask |= GICD_ICFGR_POL_LOW;
351 } else if (pol == INTR_POLARITY_HIGH) {
352 mask &= ~GICD_ICFGR_POL_MASK;
353 mask |= GICD_ICFGR_POL_HIGH;
356 if (trig == INTR_TRIGGER_LEVEL) {
357 mask &= ~GICD_ICFGR_TRIG_MASK;
358 mask |= GICD_ICFGR_TRIG_LVL;
359 } else if (trig == INTR_TRIGGER_EDGE) {
360 mask &= ~GICD_ICFGR_TRIG_MASK;
361 mask |= GICD_ICFGR_TRIG_EDGE;
365 reg = reg & ~(0x3 << 2*(irq % 16));
366 reg = reg | (mask << 2*(irq % 16));
367 gic_d_write_4(GICD_ICFGR(irq >> 4), reg);
369 mtx_unlock_spin(&arm_gic_sc->mutex);
374 device_printf(arm_gic_sc->dev, "gic_config_irg, invalid parameters\n");
380 pic_ipi_send(cpuset_t cpus, u_int ipi)
384 for (i = 0; i < MAXCPU; i++)
385 if (CPU_ISSET(i, &cpus))
386 val |= 1 << (16 + i);
387 gic_d_write_4(GICD_SGIR(0), val | ipi);
397 * The intr code will automagically give the frame pointer
398 * if the interrupt argument is 0.
400 if ((unsigned int)i > 16)
408 pic_ipi_clear(int ipi)