2 * Copyright (c) 2011 The FreeBSD Foundation
5 * Developed by Damjan Marion <damjan.marion@gmail.com>
7 * Based on OMAP4 GIC code by Ben Gray
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/module.h>
46 #include <sys/cpuset.h>
48 #include <sys/mutex.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51 #include <machine/smp.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 /* We are using GICv2 register naming */
60 /* Distributor Registers */
61 #define GICD_CTLR 0x000 /* v1 ICDDCR */
62 #define GICD_TYPER 0x004 /* v1 ICDICTR */
63 #define GICD_IIDR 0x008 /* v1 ICDIIDR */
64 #define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
65 #define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
66 #define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
67 #define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
68 #define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
69 #define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
70 #define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
71 #define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
72 #define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
73 #define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
76 #define GICC_CTLR 0x0000 /* v1 ICCICR */
77 #define GICC_PMR 0x0004 /* v1 ICCPMR */
78 #define GICC_BPR 0x0008 /* v1 ICCBPR */
79 #define GICC_IAR 0x000C /* v1 ICCIAR */
80 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
81 #define GICC_RPR 0x0014 /* v1 ICCRPR */
82 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
83 #define GICC_ABPR 0x001C /* v1 ICCABPR */
84 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
86 struct arm_gic_softc {
87 struct resource * gic_res[3];
88 bus_space_tag_t gic_c_bst;
89 bus_space_tag_t gic_d_bst;
90 bus_space_handle_t gic_c_bsh;
91 bus_space_handle_t gic_d_bsh;
95 static struct resource_spec arm_gic_spec[] = {
96 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
97 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
101 static struct arm_gic_softc *arm_gic_sc = NULL;
103 #define gic_c_read_4(reg) \
104 bus_space_read_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg)
105 #define gic_c_write_4(reg, val) \
106 bus_space_write_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg, val)
107 #define gic_d_read_4(reg) \
108 bus_space_read_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg)
109 #define gic_d_write_4(reg, val) \
110 bus_space_write_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg, val)
112 static void gic_post_filter(void *);
115 arm_gic_probe(device_t dev)
118 if (!ofw_bus_is_compatible(dev, "arm,gic"))
120 device_set_desc(dev, "ARM Generic Interrupt Controller");
121 return (BUS_PROBE_DEFAULT);
125 gic_init_secondary(void)
129 /* Get the number of interrupts */
130 nirqs = gic_d_read_4(GICD_TYPER);
131 nirqs = 32 * ((nirqs & 0x1f) + 1);
133 for (i = 0; i < nirqs; i += 4)
134 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
136 /* Set all the interrupts to be in Group 0 (secure) */
137 for (i = 0; i < nirqs; i += 32) {
138 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
141 /* Enable CPU interface */
142 gic_c_write_4(GICC_CTLR, 1);
144 /* Set priority mask register. */
145 gic_c_write_4(GICC_PMR, 0xff);
147 /* Enable interrupt distribution */
148 gic_d_write_4(GICD_CTLR, 0x01);
150 /* Activate IRQ 29, ie private timer IRQ*/
151 gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
155 arm_gic_attach(device_t dev)
157 struct arm_gic_softc *sc;
165 sc = device_get_softc(dev);
167 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
168 device_printf(dev, "could not allocate resources\n");
172 arm_post_filter = gic_post_filter;
174 /* Distributor Interface */
175 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
176 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
179 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
180 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
184 /* Disable interrupt forwarding to the CPU interface */
185 gic_d_write_4(GICD_CTLR, 0x00);
187 /* Get the number of interrupts */
188 nirqs = gic_d_read_4(GICD_TYPER);
189 nirqs = 32 * ((nirqs & 0x1f) + 1);
191 icciidr = gic_c_read_4(GICC_IIDR);
192 device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x nirqs %u\n",
193 icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
194 (icciidr & 0xfff), nirqs);
196 /* Set all global interrupts to be level triggered, active low. */
197 for (i = 32; i < nirqs; i += 32) {
198 gic_d_write_4(GICD_ICFGR(i >> 5), 0x00000000);
201 /* Disable all interrupts. */
202 for (i = 32; i < nirqs; i += 32) {
203 gic_d_write_4(GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
206 for (i = 0; i < nirqs; i += 4) {
207 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
208 gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
211 /* Set all the interrupts to be in Group 0 (secure) */
212 for (i = 0; i < nirqs; i += 32) {
213 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
216 /* Enable CPU interface */
217 gic_c_write_4(GICC_CTLR, 1);
219 /* Set priority mask register. */
220 gic_c_write_4(GICC_PMR, 0xff);
222 /* Enable interrupt distribution */
223 gic_d_write_4(GICD_CTLR, 0x01);
228 static device_method_t arm_gic_methods[] = {
229 DEVMETHOD(device_probe, arm_gic_probe),
230 DEVMETHOD(device_attach, arm_gic_attach),
234 static driver_t arm_gic_driver = {
237 sizeof(struct arm_gic_softc),
240 static devclass_t arm_gic_devclass;
242 DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0);
245 gic_post_filter(void *arg)
247 uintptr_t irq = (uintptr_t) arg;
249 gic_c_write_4(GICC_EOIR, irq);
253 arm_get_next_irq(int last_irq)
257 active_irq = gic_c_read_4(GICC_IAR);
260 * Immediatly EOIR the SGIs, because doing so requires the other
261 * bits (ie CPU number), not just the IRQ number, and we do not
262 * have this information later.
265 if ((active_irq & 0x3ff) < 16)
266 gic_c_write_4(GICC_EOIR, active_irq);
269 if (active_irq == 0x3FF) {
271 printf("Spurious interrupt detected [0x%08x]\n", active_irq);
274 gic_c_write_4(GICC_EOIR, active_irq);
280 arm_mask_irq(uintptr_t nb)
282 gic_d_write_4(GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
286 arm_unmask_irq(uintptr_t nb)
289 gic_c_write_4(GICC_EOIR, nb);
290 gic_d_write_4(GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
295 pic_ipi_send(cpuset_t cpus, u_int ipi)
299 for (i = 0; i < MAXCPU; i++)
300 if (CPU_ISSET(i, &cpus))
301 val |= 1 << (16 + i);
302 gic_d_write_4(GICD_SGIR(0), val | ipi);
312 * The intr code will automagically give the frame pointer
313 * if the interrupt argument is 0.
315 if ((unsigned int)i > 16)
323 pic_ipi_clear(int ipi)