2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2011 The FreeBSD Foundation
7 * Developed by Damjan Marion <damjan.marion@gmail.com>
9 * Based on OMAP4 GIC code by Ben Gray
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include "opt_platform.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
51 #include <sys/cpuset.h>
53 #include <sys/mutex.h>
56 #include <sys/sched.h>
62 #include <machine/bus.h>
63 #include <machine/intr.h>
64 #include <machine/smp.h>
67 #include <dev/fdt/fdt_intr.h>
68 #include <dev/ofw/ofw_bus_subr.h>
71 #include <arm/arm/gic.h>
72 #include <arm/arm/gic_common.h>
79 /* We are using GICv2 register naming */
81 /* Distributor Registers */
84 #define GICC_CTLR 0x0000 /* v1 ICCICR */
85 #define GICC_PMR 0x0004 /* v1 ICCPMR */
86 #define GICC_BPR 0x0008 /* v1 ICCBPR */
87 #define GICC_IAR 0x000C /* v1 ICCIAR */
88 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
89 #define GICC_RPR 0x0014 /* v1 ICCRPR */
90 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
91 #define GICC_ABPR 0x001C /* v1 ICCABPR */
92 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
95 #define GICD_TYPER_SECURITYEXT 0x400
96 #define GIC_SUPPORT_SECEXT(_sc) \
97 ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
100 #ifndef GIC_DEFAULT_ICFGR_INIT
101 #define GIC_DEFAULT_ICFGR_INIT 0x00000000
106 struct intr_irqsrc gi_isrc;
108 enum intr_polarity gi_pol;
109 enum intr_trigger gi_trig;
110 #define GI_FLAG_EARLY_EOI (1 << 0)
111 #define GI_FLAG_MSI (1 << 1) /* This interrupt source should only */
112 /* be used for MSI/MSI-X interrupts */
113 #define GI_FLAG_MSI_USED (1 << 2) /* This irq is already allocated */
114 /* for a MSI/MSI-X interrupt */
118 static u_int gic_irq_cpu;
119 static int arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc);
122 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
123 static u_int sgi_first_unused = GIC_FIRST_SGI;
126 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
128 static struct ofw_compat_data compat_data[] = {
129 {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */
130 {"arm,gic-400", true},
131 {"arm,cortex-a15-gic", true},
132 {"arm,cortex-a9-gic", true},
133 {"arm,cortex-a7-gic", true},
134 {"arm,arm11mp-gic", true},
135 {"brcm,brahma-b15-gic", true},
136 {"qcom,msm-qgic2", true},
141 static struct resource_spec arm_gic_spec[] = {
142 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
143 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
145 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
151 #if defined(__arm__) && defined(INVARIANTS)
152 static int gic_debug_spurious = 1;
154 static int gic_debug_spurious = 0;
156 TUNABLE_INT("hw.gic.debug_spurious", &gic_debug_spurious);
158 static u_int arm_gic_map[MAXCPU];
160 static struct arm_gic_softc *gic_sc = NULL;
162 #define gic_c_read_4(_sc, _reg) \
163 bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg))
164 #define gic_c_write_4(_sc, _reg, _val) \
165 bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val))
166 #define gic_d_read_4(_sc, _reg) \
167 bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg))
168 #define gic_d_write_1(_sc, _reg, _val) \
169 bus_space_write_1((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
170 #define gic_d_write_4(_sc, _reg, _val) \
171 bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
174 static int gic_config_irq(int irq, enum intr_trigger trig,
175 enum intr_polarity pol);
176 static void gic_post_filter(void *);
181 gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
184 gic_d_write_4(sc, GICD_ISENABLER(irq), GICD_I_MASK(irq));
188 gic_irq_mask(struct arm_gic_softc *sc, u_int irq)
191 gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq));
196 gic_cpu_mask(struct arm_gic_softc *sc)
201 /* Read the current cpuid mask by reading ITARGETSR{0..7} */
202 for (i = 0; i < 8; i++) {
203 mask = gic_d_read_4(sc, GICD_ITARGETSR(4 * i));
207 /* No mask found, assume we are on CPU interface 0 */
211 /* Collect the mask in the lower byte */
221 arm_gic_init_secondary(device_t dev)
223 struct arm_gic_softc *sc = device_get_softc(dev);
226 /* Set the mask so we can find this CPU to send it IPIs */
227 cpu = PCPU_GET(cpuid);
228 arm_gic_map[cpu] = gic_cpu_mask(sc);
230 for (irq = 0; irq < sc->nirqs; irq += 4)
231 gic_d_write_4(sc, GICD_IPRIORITYR(irq), 0);
233 /* Set all the interrupts to be in Group 0 (secure) */
234 for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) {
235 gic_d_write_4(sc, GICD_IGROUPR(irq), 0);
238 /* Enable CPU interface */
239 gic_c_write_4(sc, GICC_CTLR, 1);
241 /* Set priority mask register. */
242 gic_c_write_4(sc, GICC_PMR, 0xff);
244 /* Enable interrupt distribution */
245 gic_d_write_4(sc, GICD_CTLR, 0x01);
247 /* Unmask attached SGI interrupts. */
248 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++)
249 if (intr_isrc_init_on_cpu(GIC_INTR_ISRC(sc, irq), cpu))
250 gic_irq_unmask(sc, irq);
252 /* Unmask attached PPI interrupts. */
253 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++)
254 if (intr_isrc_init_on_cpu(GIC_INTR_ISRC(sc, irq), cpu))
255 gic_irq_unmask(sc, irq);
259 arm_gic_init_secondary(device_t dev)
261 struct arm_gic_softc *sc = device_get_softc(dev);
264 /* Set the mask so we can find this CPU to send it IPIs */
265 arm_gic_map[PCPU_GET(cpuid)] = gic_cpu_mask(sc);
267 for (i = 0; i < sc->nirqs; i += 4)
268 gic_d_write_4(sc, GICD_IPRIORITYR(i), 0);
270 /* Set all the interrupts to be in Group 0 (secure) */
271 for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
272 gic_d_write_4(sc, GICD_IGROUPR(i), 0);
275 /* Enable CPU interface */
276 gic_c_write_4(sc, GICC_CTLR, 1);
278 /* Set priority mask register. */
279 gic_c_write_4(sc, GICC_PMR, 0xff);
281 /* Enable interrupt distribution */
282 gic_d_write_4(sc, GICD_CTLR, 0x01);
285 * Activate the timer interrupts: virtual, secure, and non-secure.
287 gic_d_write_4(sc, GICD_ISENABLER(27), GICD_I_MASK(27));
288 gic_d_write_4(sc, GICD_ISENABLER(29), GICD_I_MASK(29));
289 gic_d_write_4(sc, GICD_ISENABLER(30), GICD_I_MASK(30));
296 gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
299 static u_int num_intr_cells;
300 static phandle_t self;
301 struct ofw_compat_data *ocd;
304 for (ocd = compat_data; ocd->ocd_str != NULL; ocd++) {
305 if (ofw_bus_node_is_compatible(iparent, ocd->ocd_str)) {
314 if (num_intr_cells == 0) {
315 if (OF_searchencprop(OF_node_from_xref(iparent),
316 "#interrupt-cells", &num_intr_cells,
317 sizeof(num_intr_cells)) == -1) {
322 if (num_intr_cells == 1) {
323 *interrupt = fdt32_to_cpu(intr[0]);
324 *trig = INTR_TRIGGER_CONFORM;
325 *pol = INTR_POLARITY_CONFORM;
327 if (fdt32_to_cpu(intr[0]) == 0)
328 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI;
330 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI;
332 * In intr[2], bits[3:0] are trigger type and level flags.
333 * 1 = low-to-high edge triggered
334 * 2 = high-to-low edge triggered
335 * 4 = active high level-sensitive
336 * 8 = active low level-sensitive
337 * The hardware only supports active-high-level or rising-edge
340 if (*interrupt >= GIC_FIRST_SPI &&
341 fdt32_to_cpu(intr[2]) & 0x0a) {
342 printf("unsupported trigger/polarity configuration "
343 "0x%02x\n", fdt32_to_cpu(intr[2]) & 0x0f);
345 *pol = INTR_POLARITY_CONFORM;
346 if (fdt32_to_cpu(intr[2]) & 0x03)
347 *trig = INTR_TRIGGER_EDGE;
349 *trig = INTR_TRIGGER_LEVEL;
357 arm_gic_register_isrcs(struct arm_gic_softc *sc, uint32_t num)
361 struct gic_irqsrc *irqs;
362 struct intr_irqsrc *isrc;
365 irqs = malloc(num * sizeof(struct gic_irqsrc), M_DEVBUF,
368 name = device_get_nameunit(sc->gic_dev);
369 for (irq = 0; irq < num; irq++) {
370 irqs[irq].gi_irq = irq;
371 irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
372 irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
374 isrc = &irqs[irq].gi_isrc;
375 if (irq <= GIC_LAST_SGI) {
376 error = intr_isrc_register(isrc, sc->gic_dev,
377 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
378 } else if (irq <= GIC_LAST_PPI) {
379 error = intr_isrc_register(isrc, sc->gic_dev,
380 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
382 error = intr_isrc_register(isrc, sc->gic_dev, 0,
383 "%s,s%u", name, irq - GIC_FIRST_SPI);
386 /* XXX call intr_isrc_deregister() */
387 free(irqs, M_DEVBUF);
397 arm_gic_reserve_msi_range(device_t dev, u_int start, u_int count)
399 struct arm_gic_softc *sc;
402 sc = device_get_softc(dev);
404 KASSERT((start + count) < sc->nirqs,
405 ("%s: Trying to allocate too many MSI IRQs: %d + %d > %d", __func__,
406 start, count, sc->nirqs));
407 for (i = 0; i < count; i++) {
408 KASSERT(sc->gic_irqs[start + i].gi_isrc.isrc_handlers == 0,
409 ("%s: MSI interrupt %d already has a handler", __func__,
411 KASSERT(sc->gic_irqs[start + i].gi_pol == INTR_POLARITY_CONFORM,
412 ("%s: MSI interrupt %d already has a polarity", __func__,
414 KASSERT(sc->gic_irqs[start + i].gi_trig == INTR_TRIGGER_CONFORM,
415 ("%s: MSI interrupt %d already has a trigger", __func__,
417 sc->gic_irqs[start + i].gi_pol = INTR_POLARITY_HIGH;
418 sc->gic_irqs[start + i].gi_trig = INTR_TRIGGER_EDGE;
419 sc->gic_irqs[start + i].gi_flags |= GI_FLAG_MSI;
425 arm_gic_attach(device_t dev)
427 struct arm_gic_softc *sc;
429 uint32_t icciidr, mask, nirqs;
434 sc = device_get_softc(dev);
436 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
437 device_printf(dev, "could not allocate resources\n");
444 /* Initialize mutex */
445 mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
447 /* Distributor Interface */
448 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
449 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
452 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
453 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
455 /* Disable interrupt forwarding to the CPU interface */
456 gic_d_write_4(sc, GICD_CTLR, 0x00);
458 /* Get the number of interrupts */
459 sc->typer = gic_d_read_4(sc, GICD_TYPER);
460 nirqs = GICD_TYPER_I_NUM(sc->typer);
463 if (arm_gic_register_isrcs(sc, nirqs)) {
464 device_printf(dev, "could not register irqs\n");
470 /* Set up function pointers */
471 arm_post_filter = gic_post_filter;
472 arm_config_irq = gic_config_irq;
475 icciidr = gic_c_read_4(sc, GICC_IIDR);
477 "pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
478 GICD_IIDR_PROD(icciidr), GICD_IIDR_VAR(icciidr),
479 GICD_IIDR_REV(icciidr), GICD_IIDR_IMPL(icciidr), sc->nirqs);
481 sc->gic_iidr = icciidr;
484 /* Set all global interrupts to be level triggered, active low. */
485 for (i = 32; i < sc->nirqs; i += 16) {
486 gic_d_write_4(sc, GICD_ICFGR(i), GIC_DEFAULT_ICFGR_INIT);
489 /* Disable all interrupts. */
490 for (i = 32; i < sc->nirqs; i += 32) {
491 gic_d_write_4(sc, GICD_ICENABLER(i), 0xFFFFFFFF);
494 /* Find the current cpu mask */
495 mask = gic_cpu_mask(sc);
496 /* Set the mask so we can find this CPU to send it IPIs */
497 arm_gic_map[PCPU_GET(cpuid)] = mask;
498 /* Set all four targets to this cpu */
502 for (i = 0; i < sc->nirqs; i += 4) {
503 gic_d_write_4(sc, GICD_IPRIORITYR(i), 0);
505 gic_d_write_4(sc, GICD_ITARGETSR(i), mask);
509 /* Set all the interrupts to be in Group 0 (secure) */
510 for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
511 gic_d_write_4(sc, GICD_IGROUPR(i), 0);
514 /* Enable CPU interface */
515 gic_c_write_4(sc, GICC_CTLR, 1);
517 /* Set priority mask register. */
518 gic_c_write_4(sc, GICC_PMR, 0xff);
520 /* Enable interrupt distribution */
521 gic_d_write_4(sc, GICD_CTLR, 0x01);
532 arm_gic_detach(device_t dev)
535 struct arm_gic_softc *sc;
537 sc = device_get_softc(dev);
539 if (sc->gic_irqs != NULL)
540 free(sc->gic_irqs, M_DEVBUF);
542 bus_release_resources(dev, arm_gic_spec, sc->gic_res);
550 arm_gic_print_child(device_t bus, device_t child)
552 struct resource_list *rl;
555 rv = bus_print_child_header(bus, child);
557 rl = BUS_GET_RESOURCE_LIST(bus, child);
559 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
561 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
564 rv += bus_print_child_footer(bus, child);
569 static struct resource *
570 arm_gic_alloc_resource(device_t bus, device_t child, int type, int *rid,
571 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
573 struct arm_gic_softc *sc;
574 struct resource_list_entry *rle;
575 struct resource_list *rl;
578 KASSERT(type == SYS_RES_MEMORY, ("Invalid resoure type %x", type));
580 sc = device_get_softc(bus);
583 * Request for the default allocation with a given rid: use resource
584 * list stored in the local device info.
586 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
587 rl = BUS_GET_RESOURCE_LIST(bus, child);
589 if (type == SYS_RES_IOPORT)
590 type = SYS_RES_MEMORY;
592 rle = resource_list_find(rl, type, *rid);
595 device_printf(bus, "no default resources for "
596 "rid = %d, type = %d\n", *rid, type);
604 /* Remap through ranges property */
605 for (j = 0; j < sc->nranges; j++) {
606 if (start >= sc->ranges[j].bus && end <
607 sc->ranges[j].bus + sc->ranges[j].size) {
608 start -= sc->ranges[j].bus;
609 start += sc->ranges[j].host;
610 end -= sc->ranges[j].bus;
611 end += sc->ranges[j].host;
615 if (j == sc->nranges && sc->nranges != 0) {
617 device_printf(bus, "Could not map resource "
618 "%#jx-%#jx\n", (uintmax_t)start, (uintmax_t)end);
623 return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
628 arm_gic_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
630 struct arm_gic_softc *sc;
632 sc = device_get_softc(dev);
635 case GIC_IVAR_HW_REV:
636 KASSERT(GICD_IIDR_VAR(sc->gic_iidr) < 3 &&
637 GICD_IIDR_VAR(sc->gic_iidr) != 0,
638 ("arm_gic_read_ivar: Unknown IIDR revision %u (%.08x)",
639 GICD_IIDR_VAR(sc->gic_iidr), sc->gic_iidr));
640 *result = GICD_IIDR_VAR(sc->gic_iidr);
643 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
644 ("arm_gic_read_ivar: Unknown bus type"));
645 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
646 ("arm_gic_read_ivar: Invalid bus type %u", sc->gic_bus));
647 *result = sc->gic_bus;
655 arm_gic_intr(void *arg)
657 struct arm_gic_softc *sc = arg;
658 struct gic_irqsrc *gi;
659 uint32_t irq_active_reg, irq;
660 struct trapframe *tf;
662 irq_active_reg = gic_c_read_4(sc, GICC_IAR);
663 irq = irq_active_reg & 0x3FF;
666 * 1. We do EOI here because recent read value from active interrupt
667 * register must be used for it. Another approach is to save this
668 * value into associated interrupt source.
669 * 2. EOI must be done on same CPU where interrupt has fired. Thus
670 * we must ensure that interrupted thread does not migrate to
672 * 3. EOI cannot be delayed by any preemption which could happen on
673 * critical_exit() used in MI intr code, when interrupt thread is
674 * scheduled. See next point.
675 * 4. IPI_RENDEZVOUS assumes that no preemption is permitted during
676 * an action and any use of critical_exit() could break this
677 * assumption. See comments within smp_rendezvous_action().
678 * 5. We always return FILTER_HANDLED as this is an interrupt
679 * controller dispatch function. Otherwise, in cascaded interrupt
680 * case, the whole interrupt subtree would be masked.
683 if (irq >= sc->nirqs) {
684 if (gic_debug_spurious)
685 device_printf(sc->gic_dev,
686 "Spurious interrupt detected: last irq: %d on CPU%d\n",
687 sc->last_irq[PCPU_GET(cpuid)], PCPU_GET(cpuid));
688 return (FILTER_HANDLED);
691 tf = curthread->td_intr_frame;
693 gi = sc->gic_irqs + irq;
695 * Note that GIC_FIRST_SGI is zero and is not used in 'if' statement
696 * as compiler complains that comparing u_int >= 0 is always true.
698 if (irq <= GIC_LAST_SGI) {
700 /* Call EOI for all IPI before dispatch. */
701 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
702 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
705 device_printf(sc->gic_dev, "SGI %u on UP system detected\n",
706 irq - GIC_FIRST_SGI);
707 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
712 if (gic_debug_spurious)
713 sc->last_irq[PCPU_GET(cpuid)] = irq;
714 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
715 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
717 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
718 gic_irq_mask(sc, irq);
719 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) != GI_FLAG_EARLY_EOI)
720 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
721 device_printf(sc->gic_dev, "Stray irq %u disabled\n", irq);
725 arm_irq_memory_barrier(irq);
726 irq_active_reg = gic_c_read_4(sc, GICC_IAR);
727 irq = irq_active_reg & 0x3FF;
731 return (FILTER_HANDLED);
735 gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig,
736 enum intr_polarity pol)
741 if (irq < GIC_FIRST_SPI)
744 mtx_lock_spin(&sc->mutex);
746 reg = gic_d_read_4(sc, GICD_ICFGR(irq));
747 mask = (reg >> 2*(irq % 16)) & 0x3;
749 if (pol == INTR_POLARITY_LOW) {
750 mask &= ~GICD_ICFGR_POL_MASK;
751 mask |= GICD_ICFGR_POL_LOW;
752 } else if (pol == INTR_POLARITY_HIGH) {
753 mask &= ~GICD_ICFGR_POL_MASK;
754 mask |= GICD_ICFGR_POL_HIGH;
757 if (trig == INTR_TRIGGER_LEVEL) {
758 mask &= ~GICD_ICFGR_TRIG_MASK;
759 mask |= GICD_ICFGR_TRIG_LVL;
760 } else if (trig == INTR_TRIGGER_EDGE) {
761 mask &= ~GICD_ICFGR_TRIG_MASK;
762 mask |= GICD_ICFGR_TRIG_EDGE;
766 reg = reg & ~(0x3 << 2*(irq % 16));
767 reg = reg | (mask << 2*(irq % 16));
768 gic_d_write_4(sc, GICD_ICFGR(irq), reg);
770 mtx_unlock_spin(&sc->mutex);
774 gic_bind(struct arm_gic_softc *sc, u_int irq, cpuset_t *cpus)
776 uint32_t cpu, end, mask;
778 end = min(mp_ncpus, 8);
779 for (cpu = end; cpu < MAXCPU; cpu++)
780 if (CPU_ISSET(cpu, cpus))
783 for (mask = 0, cpu = 0; cpu < end; cpu++)
784 if (CPU_ISSET(cpu, cpus))
785 mask |= arm_gic_map[cpu];
787 gic_d_write_1(sc, GICD_ITARGETSR(0) + irq, mask);
793 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
794 enum intr_polarity *polp, enum intr_trigger *trigp)
799 *polp = INTR_POLARITY_CONFORM;
800 *trigp = INTR_TRIGGER_CONFORM;
807 * The 1st cell is the interrupt type:
810 * The 2nd cell contains the interrupt number:
813 * The 3rd cell is the flags, encoded as follows:
814 * bits[3:0] trigger type and level flags
815 * 1 = low-to-high edge triggered
816 * 2 = high-to-low edge triggered
817 * 4 = active high level-sensitive
818 * 8 = active low level-sensitive
819 * bits[15:8] PPI interrupt cpu mask
820 * Each bit corresponds to each of the 8 possible cpus
821 * attached to the GIC. A bit set to '1' indicated
822 * the interrupt is wired to that CPU.
826 irq = GIC_FIRST_SPI + cells[1];
827 /* SPI irq is checked later. */
830 irq = GIC_FIRST_PPI + cells[1];
831 if (irq > GIC_LAST_PPI) {
832 device_printf(dev, "unsupported PPI interrupt "
833 "number %u\n", cells[1]);
838 device_printf(dev, "unsupported interrupt type "
839 "configuration %u\n", cells[0]);
843 tripol = cells[2] & 0xff;
844 if (tripol & 0xf0 || (tripol & FDT_INTR_LOW_MASK &&
846 device_printf(dev, "unsupported trigger/polarity "
847 "configuration 0x%02x\n", tripol);
850 *polp = INTR_POLARITY_CONFORM;
851 *trigp = tripol & FDT_INTR_EDGE_MASK ?
852 INTR_TRIGGER_EDGE : INTR_TRIGGER_LEVEL;
860 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
861 enum intr_polarity *polp, enum intr_trigger *trigp)
863 struct gic_irqsrc *gi;
865 /* Map a non-GICv2m MSI */
866 gi = (struct gic_irqsrc *)msi_data->isrc;
872 /* MSI/MSI-X interrupts are always edge triggered with high polarity */
873 *polp = INTR_POLARITY_HIGH;
874 *trigp = INTR_TRIGGER_EDGE;
880 gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
881 enum intr_polarity *polp, enum intr_trigger *trigp)
884 enum intr_polarity pol;
885 enum intr_trigger trig;
886 struct arm_gic_softc *sc;
887 struct intr_map_data_msi *dam;
889 struct intr_map_data_fdt *daf;
892 sc = device_get_softc(dev);
893 switch (data->type) {
895 case INTR_MAP_DATA_FDT:
896 daf = (struct intr_map_data_fdt *)data;
897 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
900 KASSERT(irq >= sc->nirqs ||
901 (sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) == 0,
902 ("%s: Attempting to map a MSI interrupt from FDT",
906 case INTR_MAP_DATA_MSI:
908 dam = (struct intr_map_data_msi *)data;
909 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
916 if (irq >= sc->nirqs)
918 if (pol != INTR_POLARITY_CONFORM && pol != INTR_POLARITY_LOW &&
919 pol != INTR_POLARITY_HIGH)
921 if (trig != INTR_TRIGGER_CONFORM && trig != INTR_TRIGGER_EDGE &&
922 trig != INTR_TRIGGER_LEVEL)
934 arm_gic_map_intr(device_t dev, struct intr_map_data *data,
935 struct intr_irqsrc **isrcp)
939 struct arm_gic_softc *sc;
941 error = gic_map_intr(dev, data, &irq, NULL, NULL);
943 sc = device_get_softc(dev);
944 *isrcp = GIC_INTR_ISRC(sc, irq);
950 arm_gic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
951 struct resource *res, struct intr_map_data *data)
953 struct arm_gic_softc *sc = device_get_softc(dev);
954 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
955 enum intr_trigger trig;
956 enum intr_polarity pol;
958 if ((gi->gi_flags & GI_FLAG_MSI) == GI_FLAG_MSI) {
962 KASSERT(pol == INTR_POLARITY_HIGH,
963 ("%s: MSI interrupts must be active-high", __func__));
964 KASSERT(trig == INTR_TRIGGER_EDGE,
965 ("%s: MSI interrupts must be edge triggered", __func__));
966 } else if (data != NULL) {
969 /* Get config for resource. */
970 if (gic_map_intr(dev, data, &irq, &pol, &trig) ||
974 pol = INTR_POLARITY_CONFORM;
975 trig = INTR_TRIGGER_CONFORM;
978 /* Compare config if this is not first setup. */
979 if (isrc->isrc_handlers != 0) {
980 if ((pol != INTR_POLARITY_CONFORM && pol != gi->gi_pol) ||
981 (trig != INTR_TRIGGER_CONFORM && trig != gi->gi_trig))
987 /* For MSI/MSI-X we should have already configured these */
988 if ((gi->gi_flags & GI_FLAG_MSI) == 0) {
989 if (pol == INTR_POLARITY_CONFORM)
990 pol = INTR_POLARITY_LOW; /* just pick some */
991 if (trig == INTR_TRIGGER_CONFORM)
992 trig = INTR_TRIGGER_EDGE; /* just pick some */
997 /* Edge triggered interrupts need an early EOI sent */
998 if (gi->gi_trig == INTR_TRIGGER_EDGE)
999 gi->gi_flags |= GI_FLAG_EARLY_EOI;
1003 * XXX - In case that per CPU interrupt is going to be enabled in time
1004 * when SMP is already started, we need some IPI call which
1005 * enables it on others CPUs. Further, it's more complicated as
1006 * pic_enable_source() and pic_disable_source() should act on
1007 * per CPU basis only. Thus, it should be solved here somehow.
1009 if (isrc->isrc_flags & INTR_ISRCF_PPI)
1010 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
1012 gic_config(sc, gi->gi_irq, gi->gi_trig, gi->gi_pol);
1013 arm_gic_bind_intr(dev, isrc);
1018 arm_gic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1019 struct resource *res, struct intr_map_data *data)
1021 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1023 if (isrc->isrc_handlers == 0 && (gi->gi_flags & GI_FLAG_MSI) == 0) {
1024 gi->gi_pol = INTR_POLARITY_CONFORM;
1025 gi->gi_trig = INTR_TRIGGER_CONFORM;
1031 arm_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1033 struct arm_gic_softc *sc = device_get_softc(dev);
1034 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1036 arm_irq_memory_barrier(gi->gi_irq);
1037 gic_irq_unmask(sc, gi->gi_irq);
1041 arm_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1043 struct arm_gic_softc *sc = device_get_softc(dev);
1044 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1046 gic_irq_mask(sc, gi->gi_irq);
1050 arm_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1052 struct arm_gic_softc *sc = device_get_softc(dev);
1053 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1055 arm_gic_disable_intr(dev, isrc);
1056 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq);
1060 arm_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1063 arm_irq_memory_barrier(0);
1064 arm_gic_enable_intr(dev, isrc);
1068 arm_gic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1070 struct arm_gic_softc *sc = device_get_softc(dev);
1071 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1073 /* EOI for edge-triggered done earlier. */
1074 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
1077 arm_irq_memory_barrier(0);
1078 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq);
1082 arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
1084 struct arm_gic_softc *sc = device_get_softc(dev);
1085 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1087 if (gi->gi_irq < GIC_FIRST_SPI)
1090 if (CPU_EMPTY(&isrc->isrc_cpu)) {
1091 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
1092 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
1094 return (gic_bind(sc, gi->gi_irq, &isrc->isrc_cpu));
1099 arm_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
1102 struct arm_gic_softc *sc = device_get_softc(dev);
1103 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1104 uint32_t val = 0, i;
1106 for (i = 0; i < MAXCPU; i++)
1107 if (CPU_ISSET(i, &cpus))
1108 val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT;
1110 gic_d_write_4(sc, GICD_SGIR, val | gi->gi_irq);
1114 arm_gic_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
1116 struct intr_irqsrc *isrc;
1117 struct arm_gic_softc *sc = device_get_softc(dev);
1119 if (sgi_first_unused > GIC_LAST_SGI)
1122 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
1123 sgi_to_ipi[sgi_first_unused++] = ipi;
1125 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
1133 arm_gic_next_irq(struct arm_gic_softc *sc, int last_irq)
1135 uint32_t active_irq;
1137 active_irq = gic_c_read_4(sc, GICC_IAR);
1140 * Immediately EOIR the SGIs, because doing so requires the other
1141 * bits (ie CPU number), not just the IRQ number, and we do not
1142 * have this information later.
1144 if ((active_irq & 0x3ff) <= GIC_LAST_SGI)
1145 gic_c_write_4(sc, GICC_EOIR, active_irq);
1146 active_irq &= 0x3FF;
1148 if (active_irq == 0x3FF) {
1150 device_printf(sc->gic_dev,
1151 "Spurious interrupt detected\n");
1159 arm_gic_config(device_t dev, int irq, enum intr_trigger trig,
1160 enum intr_polarity pol)
1162 struct arm_gic_softc *sc = device_get_softc(dev);
1166 /* Function is public-accessible, so validate input arguments */
1167 if ((irq < 0) || (irq >= sc->nirqs))
1169 if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
1170 (trig != INTR_TRIGGER_CONFORM))
1172 if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) &&
1173 (pol != INTR_POLARITY_CONFORM))
1176 mtx_lock_spin(&sc->mutex);
1178 reg = gic_d_read_4(sc, GICD_ICFGR(irq));
1179 mask = (reg >> 2*(irq % 16)) & 0x3;
1181 if (pol == INTR_POLARITY_LOW) {
1182 mask &= ~GICD_ICFGR_POL_MASK;
1183 mask |= GICD_ICFGR_POL_LOW;
1184 } else if (pol == INTR_POLARITY_HIGH) {
1185 mask &= ~GICD_ICFGR_POL_MASK;
1186 mask |= GICD_ICFGR_POL_HIGH;
1189 if (trig == INTR_TRIGGER_LEVEL) {
1190 mask &= ~GICD_ICFGR_TRIG_MASK;
1191 mask |= GICD_ICFGR_TRIG_LVL;
1192 } else if (trig == INTR_TRIGGER_EDGE) {
1193 mask &= ~GICD_ICFGR_TRIG_MASK;
1194 mask |= GICD_ICFGR_TRIG_EDGE;
1198 reg = reg & ~(0x3 << 2*(irq % 16));
1199 reg = reg | (mask << 2*(irq % 16));
1200 gic_d_write_4(sc, GICD_ICFGR(irq), reg);
1202 mtx_unlock_spin(&sc->mutex);
1207 device_printf(dev, "gic_config_irg, invalid parameters\n");
1213 arm_gic_mask(device_t dev, int irq)
1215 struct arm_gic_softc *sc = device_get_softc(dev);
1217 gic_d_write_4(sc, GICD_ICENABLER(irq), (1UL << (irq & 0x1F)));
1218 gic_c_write_4(sc, GICC_EOIR, irq); /* XXX - not allowed */
1222 arm_gic_unmask(device_t dev, int irq)
1224 struct arm_gic_softc *sc = device_get_softc(dev);
1226 if (irq > GIC_LAST_SGI)
1227 arm_irq_memory_barrier(irq);
1229 gic_d_write_4(sc, GICD_ISENABLER(irq), (1UL << (irq & 0x1F)));
1234 arm_gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
1236 struct arm_gic_softc *sc = device_get_softc(dev);
1237 uint32_t val = 0, i;
1239 for (i = 0; i < MAXCPU; i++)
1240 if (CPU_ISSET(i, &cpus))
1241 val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT;
1243 gic_d_write_4(sc, GICD_SGIR, val | ipi);
1247 arm_gic_ipi_read(device_t dev, int i)
1252 * The intr code will automagically give the frame pointer
1253 * if the interrupt argument is 0.
1255 if ((unsigned int)i > 16)
1264 arm_gic_ipi_clear(device_t dev, int ipi)
1271 gic_post_filter(void *arg)
1273 struct arm_gic_softc *sc = gic_sc;
1274 uintptr_t irq = (uintptr_t) arg;
1276 if (irq > GIC_LAST_SGI)
1277 arm_irq_memory_barrier(irq);
1278 gic_c_write_4(sc, GICC_EOIR, irq);
1282 gic_config_irq(int irq, enum intr_trigger trig, enum intr_polarity pol)
1285 return (arm_gic_config(gic_sc->gic_dev, irq, trig, pol));
1289 arm_mask_irq(uintptr_t nb)
1292 arm_gic_mask(gic_sc->gic_dev, nb);
1296 arm_unmask_irq(uintptr_t nb)
1299 arm_gic_unmask(gic_sc->gic_dev, nb);
1303 arm_get_next_irq(int last_irq)
1306 return (arm_gic_next_irq(gic_sc, last_irq));
1311 intr_pic_init_secondary(void)
1314 arm_gic_init_secondary(gic_sc->gic_dev);
1318 pic_ipi_send(cpuset_t cpus, u_int ipi)
1321 arm_gic_ipi_send(gic_sc->gic_dev, cpus, ipi);
1328 return (arm_gic_ipi_read(gic_sc->gic_dev, i));
1332 pic_ipi_clear(int ipi)
1335 arm_gic_ipi_clear(gic_sc->gic_dev, ipi);
1340 static device_method_t arm_gic_methods[] = {
1343 DEVMETHOD(bus_print_child, arm_gic_print_child),
1344 DEVMETHOD(bus_add_child, bus_generic_add_child),
1345 DEVMETHOD(bus_alloc_resource, arm_gic_alloc_resource),
1346 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1347 DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
1348 DEVMETHOD(bus_read_ivar, arm_gic_read_ivar),
1350 /* Interrupt controller interface */
1351 DEVMETHOD(pic_disable_intr, arm_gic_disable_intr),
1352 DEVMETHOD(pic_enable_intr, arm_gic_enable_intr),
1353 DEVMETHOD(pic_map_intr, arm_gic_map_intr),
1354 DEVMETHOD(pic_setup_intr, arm_gic_setup_intr),
1355 DEVMETHOD(pic_teardown_intr, arm_gic_teardown_intr),
1356 DEVMETHOD(pic_post_filter, arm_gic_post_filter),
1357 DEVMETHOD(pic_post_ithread, arm_gic_post_ithread),
1358 DEVMETHOD(pic_pre_ithread, arm_gic_pre_ithread),
1360 DEVMETHOD(pic_bind_intr, arm_gic_bind_intr),
1361 DEVMETHOD(pic_init_secondary, arm_gic_init_secondary),
1362 DEVMETHOD(pic_ipi_send, arm_gic_ipi_send),
1363 DEVMETHOD(pic_ipi_setup, arm_gic_ipi_setup),
1369 DEFINE_CLASS_0(gic, arm_gic_driver, arm_gic_methods,
1370 sizeof(struct arm_gic_softc));
1374 * GICv2m support -- the GICv2 MSI/MSI-X controller.
1377 #define GICV2M_MSI_TYPER 0x008
1378 #define MSI_TYPER_SPI_BASE(x) (((x) >> 16) & 0x3ff)
1379 #define MSI_TYPER_SPI_COUNT(x) (((x) >> 0) & 0x3ff)
1380 #define GICv2M_MSI_SETSPI_NS 0x040
1381 #define GICV2M_MSI_IIDR 0xFCC
1384 arm_gicv2m_attach(device_t dev)
1386 struct arm_gicv2m_softc *sc;
1390 sc = device_get_softc(dev);
1393 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1395 if (sc->sc_mem == NULL) {
1396 device_printf(dev, "Unable to allocate resources\n");
1400 typer = bus_read_4(sc->sc_mem, GICV2M_MSI_TYPER);
1401 sc->sc_spi_start = MSI_TYPER_SPI_BASE(typer);
1402 sc->sc_spi_count = MSI_TYPER_SPI_COUNT(typer);
1403 sc->sc_spi_end = sc->sc_spi_start + sc->sc_spi_count;
1405 /* Reserve these interrupts for MSI/MSI-X use */
1406 arm_gic_reserve_msi_range(device_get_parent(dev), sc->sc_spi_start,
1409 mtx_init(&sc->sc_mutex, "GICv2m lock", "", MTX_DEF);
1411 intr_msi_register(dev, sc->sc_xref);
1414 device_printf(dev, "using spi %u to %u\n", sc->sc_spi_start,
1415 sc->sc_spi_start + sc->sc_spi_count - 1);
1421 arm_gicv2m_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1422 device_t *pic, struct intr_irqsrc **srcs)
1424 struct arm_gic_softc *psc;
1425 struct arm_gicv2m_softc *sc;
1426 int i, irq, end_irq;
1429 KASSERT(powerof2(count), ("%s: bad count", __func__));
1430 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
1432 psc = device_get_softc(device_get_parent(dev));
1433 sc = device_get_softc(dev);
1435 mtx_lock(&sc->sc_mutex);
1438 for (irq = sc->sc_spi_start; irq < sc->sc_spi_end; irq++) {
1439 /* Start on an aligned interrupt */
1440 if ((irq & (maxcount - 1)) != 0)
1443 /* Assume we found a valid range until shown otherwise */
1446 /* Check this range is valid */
1447 for (end_irq = irq; end_irq != irq + count; end_irq++) {
1448 /* No free interrupts */
1449 if (end_irq == sc->sc_spi_end) {
1454 KASSERT((psc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI)!= 0,
1455 ("%s: Non-MSI interrupt found", __func__));
1457 /* This is already used */
1458 if ((psc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI_USED) ==
1468 /* Not enough interrupts were found */
1469 if (!found || irq == sc->sc_spi_end) {
1470 mtx_unlock(&sc->sc_mutex);
1474 for (i = 0; i < count; i++) {
1475 /* Mark the interrupt as used */
1476 psc->gic_irqs[irq + i].gi_flags |= GI_FLAG_MSI_USED;
1479 mtx_unlock(&sc->sc_mutex);
1481 for (i = 0; i < count; i++)
1482 srcs[i] = (struct intr_irqsrc *)&psc->gic_irqs[irq + i];
1483 *pic = device_get_parent(dev);
1489 arm_gicv2m_release_msi(device_t dev, device_t child, int count,
1490 struct intr_irqsrc **isrc)
1492 struct arm_gicv2m_softc *sc;
1493 struct gic_irqsrc *gi;
1496 sc = device_get_softc(dev);
1498 mtx_lock(&sc->sc_mutex);
1499 for (i = 0; i < count; i++) {
1500 gi = (struct gic_irqsrc *)isrc[i];
1502 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1503 ("%s: Trying to release an unused MSI-X interrupt",
1506 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1508 mtx_unlock(&sc->sc_mutex);
1514 arm_gicv2m_alloc_msix(device_t dev, device_t child, device_t *pic,
1515 struct intr_irqsrc **isrcp)
1517 struct arm_gicv2m_softc *sc;
1518 struct arm_gic_softc *psc;
1521 psc = device_get_softc(device_get_parent(dev));
1522 sc = device_get_softc(dev);
1524 mtx_lock(&sc->sc_mutex);
1525 /* Find an unused interrupt */
1526 for (irq = sc->sc_spi_start; irq < sc->sc_spi_end; irq++) {
1527 KASSERT((psc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) != 0,
1528 ("%s: Non-MSI interrupt found", __func__));
1529 if ((psc->gic_irqs[irq].gi_flags & GI_FLAG_MSI_USED) == 0)
1532 /* No free interrupt was found */
1533 if (irq == sc->sc_spi_end) {
1534 mtx_unlock(&sc->sc_mutex);
1538 /* Mark the interrupt as used */
1539 psc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI_USED;
1540 mtx_unlock(&sc->sc_mutex);
1542 *isrcp = (struct intr_irqsrc *)&psc->gic_irqs[irq];
1543 *pic = device_get_parent(dev);
1549 arm_gicv2m_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1551 struct arm_gicv2m_softc *sc;
1552 struct gic_irqsrc *gi;
1554 sc = device_get_softc(dev);
1555 gi = (struct gic_irqsrc *)isrc;
1557 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1558 ("%s: Trying to release an unused MSI-X interrupt", __func__));
1560 mtx_lock(&sc->sc_mutex);
1561 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1562 mtx_unlock(&sc->sc_mutex);
1568 arm_gicv2m_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1569 uint64_t *addr, uint32_t *data)
1571 struct arm_gicv2m_softc *sc = device_get_softc(dev);
1572 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1574 *addr = vtophys(rman_get_virtual(sc->sc_mem)) + GICv2M_MSI_SETSPI_NS;
1580 static device_method_t arm_gicv2m_methods[] = {
1581 /* Device interface */
1582 DEVMETHOD(device_attach, arm_gicv2m_attach),
1585 DEVMETHOD(msi_alloc_msi, arm_gicv2m_alloc_msi),
1586 DEVMETHOD(msi_release_msi, arm_gicv2m_release_msi),
1587 DEVMETHOD(msi_alloc_msix, arm_gicv2m_alloc_msix),
1588 DEVMETHOD(msi_release_msix, arm_gicv2m_release_msix),
1589 DEVMETHOD(msi_map_msi, arm_gicv2m_map_msi),
1595 DEFINE_CLASS_0(gicv2m, arm_gicv2m_driver, arm_gicv2m_methods,
1596 sizeof(struct arm_gicv2m_softc));