2 * Copyright (c) 2011 The FreeBSD Foundation
5 * Developed by Damjan Marion <damjan.marion@gmail.com>
7 * Based on OMAP4 GIC code by Ben Gray
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/module.h>
46 #include <sys/cpuset.h>
48 #include <sys/mutex.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51 #include <machine/smp.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 /* We are using GICv2 register naming */
60 /* Distributor Registers */
61 #define GICD_CTLR 0x000 /* v1 ICDDCR */
62 #define GICD_TYPER 0x004 /* v1 ICDICTR */
63 #define GICD_IIDR 0x008 /* v1 ICDIIDR */
64 #define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
65 #define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
66 #define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
67 #define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
68 #define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
69 #define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
70 #define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
71 #define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
72 #define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
73 #define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
76 #define GICC_CTLR 0x0000 /* v1 ICCICR */
77 #define GICC_PMR 0x0004 /* v1 ICCPMR */
78 #define GICC_BPR 0x0008 /* v1 ICCBPR */
79 #define GICC_IAR 0x000C /* v1 ICCIAR */
80 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
81 #define GICC_RPR 0x0014 /* v1 ICCRPR */
82 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
83 #define GICC_ABPR 0x001C /* v1 ICCABPR */
84 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
86 #define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */
87 #define GIC_LAST_IPI 15
88 #define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
89 #define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
90 #define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
92 /* First bit is a polarity bit (0 - low, 1 - high) */
93 #define GICD_ICFGR_POL_LOW (0 << 0)
94 #define GICD_ICFGR_POL_HIGH (1 << 0)
95 #define GICD_ICFGR_POL_MASK 0x1
96 /* Second bit is a trigger bit (0 - level, 1 - edge) */
97 #define GICD_ICFGR_TRIG_LVL (0 << 1)
98 #define GICD_ICFGR_TRIG_EDGE (1 << 1)
99 #define GICD_ICFGR_TRIG_MASK 0x2
101 #ifndef GIC_DEFAULT_ICFGR_INIT
102 #define GIC_DEFAULT_ICFGR_INIT 0x00000000
105 struct arm_gic_softc {
107 struct resource * gic_res[3];
108 bus_space_tag_t gic_c_bst;
109 bus_space_tag_t gic_d_bst;
110 bus_space_handle_t gic_c_bsh;
111 bus_space_handle_t gic_d_bsh;
117 static struct resource_spec arm_gic_spec[] = {
118 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
119 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
123 static struct arm_gic_softc *arm_gic_sc = NULL;
125 #define gic_c_read_4(_sc, _reg) \
126 bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg))
127 #define gic_c_write_4(_sc, _reg, _val) \
128 bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val))
129 #define gic_d_read_4(_sc, _reg) \
130 bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg))
131 #define gic_d_write_4(_sc, _reg, _val) \
132 bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
134 static int gic_config_irq(int irq, enum intr_trigger trig,
135 enum intr_polarity pol);
136 static void gic_post_filter(void *);
138 static struct ofw_compat_data compat_data[] = {
139 {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */
140 {"arm,gic-400", true},
141 {"arm,cortex-a15-gic", true},
142 {"arm,cortex-a9-gic", true},
143 {"arm,cortex-a7-gic", true},
144 {"arm,arm11mp-gic", true},
145 {"brcm,brahma-b15-gic", true},
150 arm_gic_probe(device_t dev)
153 if (!ofw_bus_status_okay(dev))
156 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
158 device_set_desc(dev, "ARM Generic Interrupt Controller");
159 return (BUS_PROBE_DEFAULT);
163 arm_gic_init_secondary(device_t dev)
165 struct arm_gic_softc *sc = device_get_softc(dev);
168 for (i = 0; i < sc->nirqs; i += 4)
169 gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
171 /* Set all the interrupts to be in Group 0 (secure) */
172 for (i = 0; i < sc->nirqs; i += 32) {
173 gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
176 /* Enable CPU interface */
177 gic_c_write_4(sc, GICC_CTLR, 1);
179 /* Set priority mask register. */
180 gic_c_write_4(sc, GICC_PMR, 0xff);
182 /* Enable interrupt distribution */
183 gic_d_write_4(sc, GICD_CTLR, 0x01);
186 * Activate the timer interrupts: virtual, secure, and non-secure.
188 gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
189 gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
190 gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
194 gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
197 static u_int num_intr_cells;
199 if (num_intr_cells == 0) {
200 if (OF_searchencprop(OF_node_from_xref(iparent),
201 "#interrupt-cells", &num_intr_cells,
202 sizeof(num_intr_cells)) == -1) {
207 if (num_intr_cells == 1) {
208 *interrupt = fdt32_to_cpu(intr[0]);
209 *trig = INTR_TRIGGER_CONFORM;
210 *pol = INTR_POLARITY_CONFORM;
212 if (fdt32_to_cpu(intr[0]) == 0)
213 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI;
215 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI;
217 * In intr[2], bits[3:0] are trigger type and level flags.
218 * 1 = low-to-high edge triggered
219 * 2 = high-to-low edge triggered
220 * 4 = active high level-sensitive
221 * 8 = active low level-sensitive
222 * The hardware only supports active-high-level or rising-edge.
224 if (fdt32_to_cpu(intr[2]) & 0x0a) {
225 printf("unsupported trigger/polarity configuration "
226 "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f);
229 *pol = INTR_POLARITY_CONFORM;
230 if (fdt32_to_cpu(intr[2]) & 0x01)
231 *trig = INTR_TRIGGER_EDGE;
233 *trig = INTR_TRIGGER_LEVEL;
239 arm_gic_attach(device_t dev)
241 struct arm_gic_softc *sc;
248 sc = device_get_softc(dev);
250 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
251 device_printf(dev, "could not allocate resources\n");
258 /* Initialize mutex */
259 mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
261 /* Distributor Interface */
262 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
263 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
266 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
267 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
269 /* Disable interrupt forwarding to the CPU interface */
270 gic_d_write_4(sc, GICD_CTLR, 0x00);
272 /* Get the number of interrupts */
273 sc->nirqs = gic_d_read_4(sc, GICD_TYPER);
274 sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
276 /* Set up function pointers */
277 arm_post_filter = gic_post_filter;
278 arm_config_irq = gic_config_irq;
280 icciidr = gic_c_read_4(sc, GICC_IIDR);
281 device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
282 icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
283 (icciidr & 0xfff), sc->nirqs);
285 /* Set all global interrupts to be level triggered, active low. */
286 for (i = 32; i < sc->nirqs; i += 16) {
287 gic_d_write_4(sc, GICD_ICFGR(i >> 4), GIC_DEFAULT_ICFGR_INIT);
290 /* Disable all interrupts. */
291 for (i = 32; i < sc->nirqs; i += 32) {
292 gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
295 for (i = 0; i < sc->nirqs; i += 4) {
296 gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
297 gic_d_write_4(sc, GICD_ITARGETSR(i >> 2),
298 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
301 /* Set all the interrupts to be in Group 0 (secure) */
302 for (i = 0; i < sc->nirqs; i += 32) {
303 gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
306 /* Enable CPU interface */
307 gic_c_write_4(sc, GICC_CTLR, 1);
309 /* Set priority mask register. */
310 gic_c_write_4(sc, GICC_PMR, 0xff);
312 /* Enable interrupt distribution */
313 gic_d_write_4(sc, GICD_CTLR, 0x01);
319 arm_gic_next_irq(struct arm_gic_softc *sc, int last_irq)
323 active_irq = gic_c_read_4(sc, GICC_IAR);
326 * Immediatly EOIR the SGIs, because doing so requires the other
327 * bits (ie CPU number), not just the IRQ number, and we do not
328 * have this information later.
330 if ((active_irq & 0x3ff) <= GIC_LAST_IPI)
331 gic_c_write_4(sc, GICC_EOIR, active_irq);
334 if (active_irq == 0x3FF) {
336 printf("Spurious interrupt detected\n");
344 arm_gic_config(device_t dev, int irq, enum intr_trigger trig,
345 enum intr_polarity pol)
347 struct arm_gic_softc *sc = device_get_softc(dev);
351 /* Function is public-accessible, so validate input arguments */
352 if ((irq < 0) || (irq >= sc->nirqs))
354 if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
355 (trig != INTR_TRIGGER_CONFORM))
357 if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) &&
358 (pol != INTR_POLARITY_CONFORM))
361 mtx_lock_spin(&sc->mutex);
363 reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4));
364 mask = (reg >> 2*(irq % 16)) & 0x3;
366 if (pol == INTR_POLARITY_LOW) {
367 mask &= ~GICD_ICFGR_POL_MASK;
368 mask |= GICD_ICFGR_POL_LOW;
369 } else if (pol == INTR_POLARITY_HIGH) {
370 mask &= ~GICD_ICFGR_POL_MASK;
371 mask |= GICD_ICFGR_POL_HIGH;
374 if (trig == INTR_TRIGGER_LEVEL) {
375 mask &= ~GICD_ICFGR_TRIG_MASK;
376 mask |= GICD_ICFGR_TRIG_LVL;
377 } else if (trig == INTR_TRIGGER_EDGE) {
378 mask &= ~GICD_ICFGR_TRIG_MASK;
379 mask |= GICD_ICFGR_TRIG_EDGE;
383 reg = reg & ~(0x3 << 2*(irq % 16));
384 reg = reg | (mask << 2*(irq % 16));
385 gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg);
387 mtx_unlock_spin(&sc->mutex);
392 device_printf(dev, "gic_config_irg, invalid parameters\n");
398 arm_gic_mask(device_t dev, int irq)
400 struct arm_gic_softc *sc = device_get_softc(dev);
402 gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F)));
403 gic_c_write_4(sc, GICC_EOIR, irq);
407 arm_gic_unmask(device_t dev, int irq)
409 struct arm_gic_softc *sc = device_get_softc(dev);
411 if (irq > GIC_LAST_IPI)
412 arm_irq_memory_barrier(irq);
414 gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F)));
419 arm_gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
421 struct arm_gic_softc *sc = device_get_softc(dev);
424 for (i = 0; i < MAXCPU; i++)
425 if (CPU_ISSET(i, &cpus))
426 val |= 1 << (16 + i);
428 gic_d_write_4(sc, GICD_SGIR(0), val | ipi);
432 arm_gic_ipi_read(device_t dev, int i)
437 * The intr code will automagically give the frame pointer
438 * if the interrupt argument is 0.
440 if ((unsigned int)i > 16)
449 arm_gic_ipi_clear(device_t dev, int ipi)
456 gic_post_filter(void *arg)
458 struct arm_gic_softc *sc = arm_gic_sc;
459 uintptr_t irq = (uintptr_t) arg;
461 if (irq > GIC_LAST_IPI)
462 arm_irq_memory_barrier(irq);
463 gic_c_write_4(sc, GICC_EOIR, irq);
467 gic_config_irq(int irq, enum intr_trigger trig, enum intr_polarity pol)
470 return (arm_gic_config(arm_gic_sc->gic_dev, irq, trig, pol));
474 arm_mask_irq(uintptr_t nb)
477 arm_gic_mask(arm_gic_sc->gic_dev, nb);
481 arm_unmask_irq(uintptr_t nb)
484 arm_gic_unmask(arm_gic_sc->gic_dev, nb);
488 arm_get_next_irq(int last_irq)
491 return (arm_gic_next_irq(arm_gic_sc, last_irq));
495 arm_init_secondary_ic(void)
498 arm_gic_init_secondary(arm_gic_sc->gic_dev);
503 pic_ipi_send(cpuset_t cpus, u_int ipi)
506 arm_gic_ipi_send(arm_gic_sc->gic_dev, cpus, ipi);
513 return (arm_gic_ipi_read(arm_gic_sc->gic_dev, i));
517 pic_ipi_clear(int ipi)
520 arm_gic_ipi_clear(arm_gic_sc->gic_dev, ipi);
524 static device_method_t arm_gic_methods[] = {
525 /* Device interface */
526 DEVMETHOD(device_probe, arm_gic_probe),
527 DEVMETHOD(device_attach, arm_gic_attach),
531 static driver_t arm_gic_driver = {
534 sizeof(struct arm_gic_softc),
537 static devclass_t arm_gic_devclass;
539 EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0,
540 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
541 EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0,
542 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);