2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2011 The FreeBSD Foundation
7 * Developed by Damjan Marion <damjan.marion@gmail.com>
9 * Based on OMAP4 GIC code by Ben Gray
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 #include "opt_platform.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/malloc.h>
52 #include <sys/cpuset.h>
54 #include <sys/mutex.h>
56 #include <sys/sched.h>
61 #include <machine/bus.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
66 #include <dev/fdt/fdt_intr.h>
67 #include <dev/ofw/ofw_bus_subr.h>
71 #include <contrib/dev/acpica/include/acpi.h>
72 #include <dev/acpica/acpivar.h>
75 #include <arm/arm/gic.h>
76 #include <arm/arm/gic_common.h>
81 /* We are using GICv2 register naming */
83 /* Distributor Registers */
86 #define GICC_CTLR 0x0000 /* v1 ICCICR */
87 #define GICC_PMR 0x0004 /* v1 ICCPMR */
88 #define GICC_BPR 0x0008 /* v1 ICCBPR */
89 #define GICC_IAR 0x000C /* v1 ICCIAR */
90 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
91 #define GICC_RPR 0x0014 /* v1 ICCRPR */
92 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
93 #define GICC_ABPR 0x001C /* v1 ICCABPR */
94 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
97 #define GICD_TYPER_SECURITYEXT 0x400
98 #define GIC_SUPPORT_SECEXT(_sc) \
99 ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
102 #ifndef GIC_DEFAULT_ICFGR_INIT
103 #define GIC_DEFAULT_ICFGR_INIT 0x00000000
107 struct intr_irqsrc gi_isrc;
109 enum intr_polarity gi_pol;
110 enum intr_trigger gi_trig;
111 #define GI_FLAG_EARLY_EOI (1 << 0)
112 #define GI_FLAG_MSI (1 << 1) /* This interrupt source should only */
113 /* be used for MSI/MSI-X interrupts */
114 #define GI_FLAG_MSI_USED (1 << 2) /* This irq is already allocated */
115 /* for a MSI/MSI-X interrupt */
119 static u_int gic_irq_cpu;
120 static int arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc);
123 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
124 static u_int sgi_first_unused = GIC_FIRST_SGI;
127 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
129 static struct resource_spec arm_gic_spec[] = {
130 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
131 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
132 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
137 #if defined(__arm__) && defined(INVARIANTS)
138 static int gic_debug_spurious = 1;
140 static int gic_debug_spurious = 0;
142 TUNABLE_INT("hw.gic.debug_spurious", &gic_debug_spurious);
144 static u_int arm_gic_map[MAXCPU];
146 static struct arm_gic_softc *gic_sc = NULL;
148 #define gic_c_read_4(_sc, _reg) \
149 bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg))
150 #define gic_c_write_4(_sc, _reg, _val) \
151 bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val))
152 #define gic_d_read_4(_sc, _reg) \
153 bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg))
154 #define gic_d_write_1(_sc, _reg, _val) \
155 bus_space_write_1((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
156 #define gic_d_write_4(_sc, _reg, _val) \
157 bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
160 gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
163 gic_d_write_4(sc, GICD_ISENABLER(irq), GICD_I_MASK(irq));
167 gic_irq_mask(struct arm_gic_softc *sc, u_int irq)
170 gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq));
174 gic_cpu_mask(struct arm_gic_softc *sc)
179 /* Read the current cpuid mask by reading ITARGETSR{0..7} */
180 for (i = 0; i < 8; i++) {
181 mask = gic_d_read_4(sc, GICD_ITARGETSR(4 * i));
185 /* No mask found, assume we are on CPU interface 0 */
189 /* Collect the mask in the lower byte */
198 arm_gic_init_secondary(device_t dev)
200 struct arm_gic_softc *sc = device_get_softc(dev);
203 /* Set the mask so we can find this CPU to send it IPIs */
204 cpu = PCPU_GET(cpuid);
205 arm_gic_map[cpu] = gic_cpu_mask(sc);
207 for (irq = 0; irq < sc->nirqs; irq += 4)
208 gic_d_write_4(sc, GICD_IPRIORITYR(irq), 0);
210 /* Set all the interrupts to be in Group 0 (secure) */
211 for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) {
212 gic_d_write_4(sc, GICD_IGROUPR(irq), 0);
215 /* Enable CPU interface */
216 gic_c_write_4(sc, GICC_CTLR, 1);
218 /* Set priority mask register. */
219 gic_c_write_4(sc, GICC_PMR, 0xff);
221 /* Enable interrupt distribution */
222 gic_d_write_4(sc, GICD_CTLR, 0x01);
224 /* Unmask attached SGI interrupts. */
225 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++)
226 if (intr_isrc_init_on_cpu(GIC_INTR_ISRC(sc, irq), cpu))
227 gic_irq_unmask(sc, irq);
229 /* Unmask attached PPI interrupts. */
230 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++)
231 if (intr_isrc_init_on_cpu(GIC_INTR_ISRC(sc, irq), cpu))
232 gic_irq_unmask(sc, irq);
237 arm_gic_register_isrcs(struct arm_gic_softc *sc, uint32_t num)
241 struct gic_irqsrc *irqs;
242 struct intr_irqsrc *isrc;
245 irqs = malloc(num * sizeof(struct gic_irqsrc), M_DEVBUF,
248 name = device_get_nameunit(sc->gic_dev);
249 for (irq = 0; irq < num; irq++) {
250 irqs[irq].gi_irq = irq;
251 irqs[irq].gi_pol = INTR_POLARITY_CONFORM;
252 irqs[irq].gi_trig = INTR_TRIGGER_CONFORM;
254 isrc = &irqs[irq].gi_isrc;
255 if (irq <= GIC_LAST_SGI) {
256 error = intr_isrc_register(isrc, sc->gic_dev,
257 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI);
258 } else if (irq <= GIC_LAST_PPI) {
259 error = intr_isrc_register(isrc, sc->gic_dev,
260 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI);
262 error = intr_isrc_register(isrc, sc->gic_dev, 0,
263 "%s,s%u", name, irq - GIC_FIRST_SPI);
266 /* XXX call intr_isrc_deregister() */
267 free(irqs, M_DEVBUF);
277 arm_gic_reserve_msi_range(device_t dev, u_int start, u_int count)
279 struct arm_gic_softc *sc;
282 sc = device_get_softc(dev);
284 KASSERT((start + count) < sc->nirqs,
285 ("%s: Trying to allocate too many MSI IRQs: %d + %d > %d", __func__,
286 start, count, sc->nirqs));
287 for (i = 0; i < count; i++) {
288 KASSERT(sc->gic_irqs[start + i].gi_isrc.isrc_handlers == 0,
289 ("%s: MSI interrupt %d already has a handler", __func__,
291 KASSERT(sc->gic_irqs[start + i].gi_pol == INTR_POLARITY_CONFORM,
292 ("%s: MSI interrupt %d already has a polarity", __func__,
294 KASSERT(sc->gic_irqs[start + i].gi_trig == INTR_TRIGGER_CONFORM,
295 ("%s: MSI interrupt %d already has a trigger", __func__,
297 sc->gic_irqs[start + i].gi_pol = INTR_POLARITY_HIGH;
298 sc->gic_irqs[start + i].gi_trig = INTR_TRIGGER_EDGE;
299 sc->gic_irqs[start + i].gi_flags |= GI_FLAG_MSI;
304 arm_gic_attach(device_t dev)
306 struct arm_gic_softc *sc;
308 uint32_t icciidr, mask, nirqs;
313 sc = device_get_softc(dev);
315 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
316 device_printf(dev, "could not allocate resources\n");
323 /* Initialize mutex */
324 mtx_init(&sc->mutex, "GIC lock", NULL, MTX_SPIN);
326 /* Distributor Interface */
327 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
328 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
331 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
332 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
334 /* Disable interrupt forwarding to the CPU interface */
335 gic_d_write_4(sc, GICD_CTLR, 0x00);
337 /* Get the number of interrupts */
338 sc->typer = gic_d_read_4(sc, GICD_TYPER);
339 nirqs = GICD_TYPER_I_NUM(sc->typer);
341 if (arm_gic_register_isrcs(sc, nirqs)) {
342 device_printf(dev, "could not register irqs\n");
346 icciidr = gic_c_read_4(sc, GICC_IIDR);
348 "pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
349 GICD_IIDR_PROD(icciidr), GICD_IIDR_VAR(icciidr),
350 GICD_IIDR_REV(icciidr), GICD_IIDR_IMPL(icciidr), sc->nirqs);
351 sc->gic_iidr = icciidr;
353 /* Set all global interrupts to be level triggered, active low. */
354 for (i = 32; i < sc->nirqs; i += 16) {
355 gic_d_write_4(sc, GICD_ICFGR(i), GIC_DEFAULT_ICFGR_INIT);
358 /* Disable all interrupts. */
359 for (i = 32; i < sc->nirqs; i += 32) {
360 gic_d_write_4(sc, GICD_ICENABLER(i), 0xFFFFFFFF);
363 /* Find the current cpu mask */
364 mask = gic_cpu_mask(sc);
365 /* Set the mask so we can find this CPU to send it IPIs */
366 arm_gic_map[PCPU_GET(cpuid)] = mask;
367 /* Set all four targets to this cpu */
371 for (i = 0; i < sc->nirqs; i += 4) {
372 gic_d_write_4(sc, GICD_IPRIORITYR(i), 0);
374 gic_d_write_4(sc, GICD_ITARGETSR(i), mask);
378 /* Set all the interrupts to be in Group 0 (secure) */
379 for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
380 gic_d_write_4(sc, GICD_IGROUPR(i), 0);
383 /* Enable CPU interface */
384 gic_c_write_4(sc, GICC_CTLR, 1);
386 /* Set priority mask register. */
387 gic_c_write_4(sc, GICC_PMR, 0xff);
389 /* Enable interrupt distribution */
390 gic_d_write_4(sc, GICD_CTLR, 0x01);
399 arm_gic_detach(device_t dev)
401 struct arm_gic_softc *sc;
403 sc = device_get_softc(dev);
405 if (sc->gic_irqs != NULL)
406 free(sc->gic_irqs, M_DEVBUF);
408 bus_release_resources(dev, arm_gic_spec, sc->gic_res);
414 arm_gic_print_child(device_t bus, device_t child)
416 struct resource_list *rl;
419 rv = bus_print_child_header(bus, child);
421 rl = BUS_GET_RESOURCE_LIST(bus, child);
423 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
425 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
428 rv += bus_print_child_footer(bus, child);
433 static struct resource *
434 arm_gic_alloc_resource(device_t bus, device_t child, int type, int *rid,
435 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
437 struct arm_gic_softc *sc;
438 struct resource_list_entry *rle;
439 struct resource_list *rl;
442 KASSERT(type == SYS_RES_MEMORY, ("Invalid resoure type %x", type));
444 sc = device_get_softc(bus);
447 * Request for the default allocation with a given rid: use resource
448 * list stored in the local device info.
450 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
451 rl = BUS_GET_RESOURCE_LIST(bus, child);
453 if (type == SYS_RES_IOPORT)
454 type = SYS_RES_MEMORY;
456 rle = resource_list_find(rl, type, *rid);
459 device_printf(bus, "no default resources for "
460 "rid = %d, type = %d\n", *rid, type);
468 /* Remap through ranges property */
469 for (j = 0; j < sc->nranges; j++) {
470 if (start >= sc->ranges[j].bus && end <
471 sc->ranges[j].bus + sc->ranges[j].size) {
472 start -= sc->ranges[j].bus;
473 start += sc->ranges[j].host;
474 end -= sc->ranges[j].bus;
475 end += sc->ranges[j].host;
479 if (j == sc->nranges && sc->nranges != 0) {
481 device_printf(bus, "Could not map resource "
482 "%#jx-%#jx\n", (uintmax_t)start, (uintmax_t)end);
487 return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
492 arm_gic_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
494 struct arm_gic_softc *sc;
496 sc = device_get_softc(dev);
499 case GIC_IVAR_HW_REV:
500 KASSERT(GICD_IIDR_VAR(sc->gic_iidr) < 3 &&
501 GICD_IIDR_VAR(sc->gic_iidr) != 0,
502 ("arm_gic_read_ivar: Unknown IIDR revision %u (%.08x)",
503 GICD_IIDR_VAR(sc->gic_iidr), sc->gic_iidr));
504 *result = GICD_IIDR_VAR(sc->gic_iidr);
507 KASSERT(sc->gic_bus != GIC_BUS_UNKNOWN,
508 ("arm_gic_read_ivar: Unknown bus type"));
509 KASSERT(sc->gic_bus <= GIC_BUS_MAX,
510 ("arm_gic_read_ivar: Invalid bus type %u", sc->gic_bus));
511 *result = sc->gic_bus;
519 arm_gic_intr(void *arg)
521 struct arm_gic_softc *sc = arg;
522 struct gic_irqsrc *gi;
523 uint32_t irq_active_reg, irq;
524 struct trapframe *tf;
526 irq_active_reg = gic_c_read_4(sc, GICC_IAR);
527 irq = irq_active_reg & 0x3FF;
530 * 1. We do EOI here because recent read value from active interrupt
531 * register must be used for it. Another approach is to save this
532 * value into associated interrupt source.
533 * 2. EOI must be done on same CPU where interrupt has fired. Thus
534 * we must ensure that interrupted thread does not migrate to
536 * 3. EOI cannot be delayed by any preemption which could happen on
537 * critical_exit() used in MI intr code, when interrupt thread is
538 * scheduled. See next point.
539 * 4. IPI_RENDEZVOUS assumes that no preemption is permitted during
540 * an action and any use of critical_exit() could break this
541 * assumption. See comments within smp_rendezvous_action().
542 * 5. We always return FILTER_HANDLED as this is an interrupt
543 * controller dispatch function. Otherwise, in cascaded interrupt
544 * case, the whole interrupt subtree would be masked.
547 if (irq >= sc->nirqs) {
548 if (gic_debug_spurious)
549 device_printf(sc->gic_dev,
550 "Spurious interrupt detected: last irq: %d on CPU%d\n",
551 sc->last_irq[PCPU_GET(cpuid)], PCPU_GET(cpuid));
552 return (FILTER_HANDLED);
555 tf = curthread->td_intr_frame;
557 gi = sc->gic_irqs + irq;
559 * Note that GIC_FIRST_SGI is zero and is not used in 'if' statement
560 * as compiler complains that comparing u_int >= 0 is always true.
562 if (irq <= GIC_LAST_SGI) {
564 /* Call EOI for all IPI before dispatch. */
565 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
566 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf);
569 device_printf(sc->gic_dev, "SGI %u on UP system detected\n",
570 irq - GIC_FIRST_SGI);
571 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
576 if (gic_debug_spurious)
577 sc->last_irq[PCPU_GET(cpuid)] = irq;
578 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
579 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
581 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
582 gic_irq_mask(sc, irq);
583 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) != GI_FLAG_EARLY_EOI)
584 gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
585 device_printf(sc->gic_dev, "Stray irq %u disabled\n", irq);
589 arm_irq_memory_barrier(irq);
590 irq_active_reg = gic_c_read_4(sc, GICC_IAR);
591 irq = irq_active_reg & 0x3FF;
595 return (FILTER_HANDLED);
599 gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig,
600 enum intr_polarity pol)
605 if (irq < GIC_FIRST_SPI)
608 mtx_lock_spin(&sc->mutex);
610 reg = gic_d_read_4(sc, GICD_ICFGR(irq));
611 mask = (reg >> 2*(irq % 16)) & 0x3;
613 if (pol == INTR_POLARITY_LOW) {
614 mask &= ~GICD_ICFGR_POL_MASK;
615 mask |= GICD_ICFGR_POL_LOW;
616 } else if (pol == INTR_POLARITY_HIGH) {
617 mask &= ~GICD_ICFGR_POL_MASK;
618 mask |= GICD_ICFGR_POL_HIGH;
621 if (trig == INTR_TRIGGER_LEVEL) {
622 mask &= ~GICD_ICFGR_TRIG_MASK;
623 mask |= GICD_ICFGR_TRIG_LVL;
624 } else if (trig == INTR_TRIGGER_EDGE) {
625 mask &= ~GICD_ICFGR_TRIG_MASK;
626 mask |= GICD_ICFGR_TRIG_EDGE;
630 reg = reg & ~(0x3 << 2*(irq % 16));
631 reg = reg | (mask << 2*(irq % 16));
632 gic_d_write_4(sc, GICD_ICFGR(irq), reg);
634 mtx_unlock_spin(&sc->mutex);
638 gic_bind(struct arm_gic_softc *sc, u_int irq, cpuset_t *cpus)
640 uint32_t cpu, end, mask;
642 end = min(mp_ncpus, 8);
643 for (cpu = end; cpu < MAXCPU; cpu++)
644 if (CPU_ISSET(cpu, cpus))
647 for (mask = 0, cpu = 0; cpu < end; cpu++)
648 if (CPU_ISSET(cpu, cpus))
649 mask |= arm_gic_map[cpu];
651 gic_d_write_1(sc, GICD_ITARGETSR(0) + irq, mask);
657 gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
658 enum intr_polarity *polp, enum intr_trigger *trigp)
663 *polp = INTR_POLARITY_CONFORM;
664 *trigp = INTR_TRIGGER_CONFORM;
671 * The 1st cell is the interrupt type:
674 * The 2nd cell contains the interrupt number:
677 * The 3rd cell is the flags, encoded as follows:
678 * bits[3:0] trigger type and level flags
679 * 1 = low-to-high edge triggered
680 * 2 = high-to-low edge triggered
681 * 4 = active high level-sensitive
682 * 8 = active low level-sensitive
683 * bits[15:8] PPI interrupt cpu mask
684 * Each bit corresponds to each of the 8 possible cpus
685 * attached to the GIC. A bit set to '1' indicated
686 * the interrupt is wired to that CPU.
690 irq = GIC_FIRST_SPI + cells[1];
691 /* SPI irq is checked later. */
694 irq = GIC_FIRST_PPI + cells[1];
695 if (irq > GIC_LAST_PPI) {
696 device_printf(dev, "unsupported PPI interrupt "
697 "number %u\n", cells[1]);
702 device_printf(dev, "unsupported interrupt type "
703 "configuration %u\n", cells[0]);
707 tripol = cells[2] & 0xff;
708 if (tripol & 0xf0 || (tripol & FDT_INTR_LOW_MASK &&
710 device_printf(dev, "unsupported trigger/polarity "
711 "configuration 0x%02x\n", tripol);
714 *polp = INTR_POLARITY_CONFORM;
715 *trigp = tripol & FDT_INTR_EDGE_MASK ?
716 INTR_TRIGGER_EDGE : INTR_TRIGGER_LEVEL;
724 gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
725 enum intr_polarity *polp, enum intr_trigger *trigp)
727 struct gic_irqsrc *gi;
729 /* Map a non-GICv2m MSI */
730 gi = (struct gic_irqsrc *)msi_data->isrc;
736 /* MSI/MSI-X interrupts are always edge triggered with high polarity */
737 *polp = INTR_POLARITY_HIGH;
738 *trigp = INTR_TRIGGER_EDGE;
744 gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
745 enum intr_polarity *polp, enum intr_trigger *trigp)
748 enum intr_polarity pol;
749 enum intr_trigger trig;
750 struct arm_gic_softc *sc;
751 struct intr_map_data_msi *dam;
753 struct intr_map_data_fdt *daf;
756 struct intr_map_data_acpi *daa;
759 sc = device_get_softc(dev);
760 switch (data->type) {
762 case INTR_MAP_DATA_FDT:
763 daf = (struct intr_map_data_fdt *)data;
764 if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol,
767 KASSERT(irq >= sc->nirqs ||
768 (sc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) == 0,
769 ("%s: Attempting to map a MSI interrupt from FDT",
774 case INTR_MAP_DATA_ACPI:
775 daa = (struct intr_map_data_acpi *)data;
781 case INTR_MAP_DATA_MSI:
783 dam = (struct intr_map_data_msi *)data;
784 if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
791 if (irq >= sc->nirqs)
793 if (pol != INTR_POLARITY_CONFORM && pol != INTR_POLARITY_LOW &&
794 pol != INTR_POLARITY_HIGH)
796 if (trig != INTR_TRIGGER_CONFORM && trig != INTR_TRIGGER_EDGE &&
797 trig != INTR_TRIGGER_LEVEL)
809 arm_gic_map_intr(device_t dev, struct intr_map_data *data,
810 struct intr_irqsrc **isrcp)
814 struct arm_gic_softc *sc;
816 error = gic_map_intr(dev, data, &irq, NULL, NULL);
818 sc = device_get_softc(dev);
819 *isrcp = GIC_INTR_ISRC(sc, irq);
825 arm_gic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
826 struct resource *res, struct intr_map_data *data)
828 struct arm_gic_softc *sc = device_get_softc(dev);
829 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
830 enum intr_trigger trig;
831 enum intr_polarity pol;
833 if ((gi->gi_flags & GI_FLAG_MSI) == GI_FLAG_MSI) {
837 KASSERT(pol == INTR_POLARITY_HIGH,
838 ("%s: MSI interrupts must be active-high", __func__));
839 KASSERT(trig == INTR_TRIGGER_EDGE,
840 ("%s: MSI interrupts must be edge triggered", __func__));
841 } else if (data != NULL) {
844 /* Get config for resource. */
845 if (gic_map_intr(dev, data, &irq, &pol, &trig) ||
849 pol = INTR_POLARITY_CONFORM;
850 trig = INTR_TRIGGER_CONFORM;
853 /* Compare config if this is not first setup. */
854 if (isrc->isrc_handlers != 0) {
855 if ((pol != INTR_POLARITY_CONFORM && pol != gi->gi_pol) ||
856 (trig != INTR_TRIGGER_CONFORM && trig != gi->gi_trig))
862 /* For MSI/MSI-X we should have already configured these */
863 if ((gi->gi_flags & GI_FLAG_MSI) == 0) {
864 if (pol == INTR_POLARITY_CONFORM)
865 pol = INTR_POLARITY_LOW; /* just pick some */
866 if (trig == INTR_TRIGGER_CONFORM)
867 trig = INTR_TRIGGER_EDGE; /* just pick some */
872 /* Edge triggered interrupts need an early EOI sent */
873 if (gi->gi_trig == INTR_TRIGGER_EDGE)
874 gi->gi_flags |= GI_FLAG_EARLY_EOI;
878 * XXX - In case that per CPU interrupt is going to be enabled in time
879 * when SMP is already started, we need some IPI call which
880 * enables it on others CPUs. Further, it's more complicated as
881 * pic_enable_source() and pic_disable_source() should act on
882 * per CPU basis only. Thus, it should be solved here somehow.
884 if (isrc->isrc_flags & INTR_ISRCF_PPI)
885 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
887 gic_config(sc, gi->gi_irq, gi->gi_trig, gi->gi_pol);
888 arm_gic_bind_intr(dev, isrc);
893 arm_gic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
894 struct resource *res, struct intr_map_data *data)
896 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
898 if (isrc->isrc_handlers == 0 && (gi->gi_flags & GI_FLAG_MSI) == 0) {
899 gi->gi_pol = INTR_POLARITY_CONFORM;
900 gi->gi_trig = INTR_TRIGGER_CONFORM;
906 arm_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
908 struct arm_gic_softc *sc = device_get_softc(dev);
909 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
911 arm_irq_memory_barrier(gi->gi_irq);
912 gic_irq_unmask(sc, gi->gi_irq);
916 arm_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
918 struct arm_gic_softc *sc = device_get_softc(dev);
919 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
921 gic_irq_mask(sc, gi->gi_irq);
925 arm_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
927 struct arm_gic_softc *sc = device_get_softc(dev);
928 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
930 arm_gic_disable_intr(dev, isrc);
931 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq);
935 arm_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
938 arm_irq_memory_barrier(0);
939 arm_gic_enable_intr(dev, isrc);
943 arm_gic_post_filter(device_t dev, struct intr_irqsrc *isrc)
945 struct arm_gic_softc *sc = device_get_softc(dev);
946 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
948 /* EOI for edge-triggered done earlier. */
949 if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
952 arm_irq_memory_barrier(0);
953 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq);
957 arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
959 struct arm_gic_softc *sc = device_get_softc(dev);
960 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
962 if (gi->gi_irq < GIC_FIRST_SPI)
965 if (CPU_EMPTY(&isrc->isrc_cpu)) {
966 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus);
967 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
969 return (gic_bind(sc, gi->gi_irq, &isrc->isrc_cpu));
974 arm_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
977 struct arm_gic_softc *sc = device_get_softc(dev);
978 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
981 for (i = 0; i < MAXCPU; i++)
982 if (CPU_ISSET(i, &cpus))
983 val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT;
985 gic_d_write_4(sc, GICD_SGIR, val | gi->gi_irq);
989 arm_gic_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
991 struct intr_irqsrc *isrc;
992 struct arm_gic_softc *sc = device_get_softc(dev);
994 if (sgi_first_unused > GIC_LAST_SGI)
997 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
998 sgi_to_ipi[sgi_first_unused++] = ipi;
1000 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
1007 static device_method_t arm_gic_methods[] = {
1009 DEVMETHOD(bus_print_child, arm_gic_print_child),
1010 DEVMETHOD(bus_add_child, bus_generic_add_child),
1011 DEVMETHOD(bus_alloc_resource, arm_gic_alloc_resource),
1012 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1013 DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
1014 DEVMETHOD(bus_read_ivar, arm_gic_read_ivar),
1016 /* Interrupt controller interface */
1017 DEVMETHOD(pic_disable_intr, arm_gic_disable_intr),
1018 DEVMETHOD(pic_enable_intr, arm_gic_enable_intr),
1019 DEVMETHOD(pic_map_intr, arm_gic_map_intr),
1020 DEVMETHOD(pic_setup_intr, arm_gic_setup_intr),
1021 DEVMETHOD(pic_teardown_intr, arm_gic_teardown_intr),
1022 DEVMETHOD(pic_post_filter, arm_gic_post_filter),
1023 DEVMETHOD(pic_post_ithread, arm_gic_post_ithread),
1024 DEVMETHOD(pic_pre_ithread, arm_gic_pre_ithread),
1026 DEVMETHOD(pic_bind_intr, arm_gic_bind_intr),
1027 DEVMETHOD(pic_init_secondary, arm_gic_init_secondary),
1028 DEVMETHOD(pic_ipi_send, arm_gic_ipi_send),
1029 DEVMETHOD(pic_ipi_setup, arm_gic_ipi_setup),
1034 DEFINE_CLASS_0(gic, arm_gic_driver, arm_gic_methods,
1035 sizeof(struct arm_gic_softc));
1038 * GICv2m support -- the GICv2 MSI/MSI-X controller.
1041 #define GICV2M_MSI_TYPER 0x008
1042 #define MSI_TYPER_SPI_BASE(x) (((x) >> 16) & 0x3ff)
1043 #define MSI_TYPER_SPI_COUNT(x) (((x) >> 0) & 0x3ff)
1044 #define GICv2M_MSI_SETSPI_NS 0x040
1045 #define GICV2M_MSI_IIDR 0xFCC
1048 arm_gicv2m_attach(device_t dev)
1050 struct arm_gicv2m_softc *sc;
1054 sc = device_get_softc(dev);
1057 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1059 if (sc->sc_mem == NULL) {
1060 device_printf(dev, "Unable to allocate resources\n");
1064 typer = bus_read_4(sc->sc_mem, GICV2M_MSI_TYPER);
1065 sc->sc_spi_start = MSI_TYPER_SPI_BASE(typer);
1066 sc->sc_spi_count = MSI_TYPER_SPI_COUNT(typer);
1067 sc->sc_spi_end = sc->sc_spi_start + sc->sc_spi_count;
1069 /* Reserve these interrupts for MSI/MSI-X use */
1070 arm_gic_reserve_msi_range(device_get_parent(dev), sc->sc_spi_start,
1073 mtx_init(&sc->sc_mutex, "GICv2m lock", NULL, MTX_DEF);
1075 intr_msi_register(dev, sc->sc_xref);
1078 device_printf(dev, "using spi %u to %u\n", sc->sc_spi_start,
1079 sc->sc_spi_start + sc->sc_spi_count - 1);
1085 arm_gicv2m_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1086 device_t *pic, struct intr_irqsrc **srcs)
1088 struct arm_gic_softc *psc;
1089 struct arm_gicv2m_softc *sc;
1090 int i, irq, end_irq;
1093 KASSERT(powerof2(count), ("%s: bad count", __func__));
1094 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
1096 psc = device_get_softc(device_get_parent(dev));
1097 sc = device_get_softc(dev);
1099 mtx_lock(&sc->sc_mutex);
1102 for (irq = sc->sc_spi_start; irq < sc->sc_spi_end; irq++) {
1103 /* Start on an aligned interrupt */
1104 if ((irq & (maxcount - 1)) != 0)
1107 /* Assume we found a valid range until shown otherwise */
1110 /* Check this range is valid */
1111 for (end_irq = irq; end_irq != irq + count; end_irq++) {
1112 /* No free interrupts */
1113 if (end_irq == sc->sc_spi_end) {
1118 KASSERT((psc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI)!= 0,
1119 ("%s: Non-MSI interrupt found", __func__));
1121 /* This is already used */
1122 if ((psc->gic_irqs[end_irq].gi_flags & GI_FLAG_MSI_USED) ==
1132 /* Not enough interrupts were found */
1133 if (!found || irq == sc->sc_spi_end) {
1134 mtx_unlock(&sc->sc_mutex);
1138 for (i = 0; i < count; i++) {
1139 /* Mark the interrupt as used */
1140 psc->gic_irqs[irq + i].gi_flags |= GI_FLAG_MSI_USED;
1143 mtx_unlock(&sc->sc_mutex);
1145 for (i = 0; i < count; i++)
1146 srcs[i] = (struct intr_irqsrc *)&psc->gic_irqs[irq + i];
1147 *pic = device_get_parent(dev);
1153 arm_gicv2m_release_msi(device_t dev, device_t child, int count,
1154 struct intr_irqsrc **isrc)
1156 struct arm_gicv2m_softc *sc;
1157 struct gic_irqsrc *gi;
1160 sc = device_get_softc(dev);
1162 mtx_lock(&sc->sc_mutex);
1163 for (i = 0; i < count; i++) {
1164 gi = (struct gic_irqsrc *)isrc[i];
1166 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1167 ("%s: Trying to release an unused MSI-X interrupt",
1170 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1172 mtx_unlock(&sc->sc_mutex);
1178 arm_gicv2m_alloc_msix(device_t dev, device_t child, device_t *pic,
1179 struct intr_irqsrc **isrcp)
1181 struct arm_gicv2m_softc *sc;
1182 struct arm_gic_softc *psc;
1185 psc = device_get_softc(device_get_parent(dev));
1186 sc = device_get_softc(dev);
1188 mtx_lock(&sc->sc_mutex);
1189 /* Find an unused interrupt */
1190 for (irq = sc->sc_spi_start; irq < sc->sc_spi_end; irq++) {
1191 KASSERT((psc->gic_irqs[irq].gi_flags & GI_FLAG_MSI) != 0,
1192 ("%s: Non-MSI interrupt found", __func__));
1193 if ((psc->gic_irqs[irq].gi_flags & GI_FLAG_MSI_USED) == 0)
1196 /* No free interrupt was found */
1197 if (irq == sc->sc_spi_end) {
1198 mtx_unlock(&sc->sc_mutex);
1202 /* Mark the interrupt as used */
1203 psc->gic_irqs[irq].gi_flags |= GI_FLAG_MSI_USED;
1204 mtx_unlock(&sc->sc_mutex);
1206 *isrcp = (struct intr_irqsrc *)&psc->gic_irqs[irq];
1207 *pic = device_get_parent(dev);
1213 arm_gicv2m_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1215 struct arm_gicv2m_softc *sc;
1216 struct gic_irqsrc *gi;
1218 sc = device_get_softc(dev);
1219 gi = (struct gic_irqsrc *)isrc;
1221 KASSERT((gi->gi_flags & GI_FLAG_MSI_USED) == GI_FLAG_MSI_USED,
1222 ("%s: Trying to release an unused MSI-X interrupt", __func__));
1224 mtx_lock(&sc->sc_mutex);
1225 gi->gi_flags &= ~GI_FLAG_MSI_USED;
1226 mtx_unlock(&sc->sc_mutex);
1232 arm_gicv2m_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1233 uint64_t *addr, uint32_t *data)
1235 struct arm_gicv2m_softc *sc = device_get_softc(dev);
1236 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
1238 *addr = vtophys(rman_get_virtual(sc->sc_mem)) + GICv2M_MSI_SETSPI_NS;
1244 static device_method_t arm_gicv2m_methods[] = {
1245 /* Device interface */
1246 DEVMETHOD(device_attach, arm_gicv2m_attach),
1249 DEVMETHOD(msi_alloc_msi, arm_gicv2m_alloc_msi),
1250 DEVMETHOD(msi_release_msi, arm_gicv2m_release_msi),
1251 DEVMETHOD(msi_alloc_msix, arm_gicv2m_alloc_msix),
1252 DEVMETHOD(msi_release_msix, arm_gicv2m_release_msix),
1253 DEVMETHOD(msi_map_msi, arm_gicv2m_map_msi),
1259 DEFINE_CLASS_0(gicv2m, arm_gicv2m_driver, arm_gicv2m_methods,
1260 sizeof(struct arm_gicv2m_softc));