1 /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */
4 * Copyright (c) 1995 Mark Brinicombe.
5 * Copyright (c) 1995 Brini.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Probing and configuration for the master CPU
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <machine/cpu.h>
52 #include <machine/md_var.h>
54 char machine[] = "arm";
56 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
57 machine, 0, "Machine class");
59 static char cpu_model[64];
60 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
61 cpu_model, sizeof(cpu_model), "Machine model");
63 static char hw_buf[81];
64 static int hw_buf_idx;
65 static bool hw_buf_newline;
67 enum cpu_class cpu_class = CPU_CLASS_NONE;
74 enum cpu_class cpu_class;
76 {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176",
78 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
80 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
82 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
84 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
86 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
88 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
90 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
92 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
94 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
96 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72",
98 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
101 {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7",
103 {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7",
106 {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
113 uint32_t isize, dsize;
118 int picache_line_size;
121 int pdcache_line_size;
126 picache_line_size = 0 ;
129 pdcache_line_size = 0;
132 if ((cpuinfo.ctr & CPU_CT_S) == 0)
136 * If you want to know how this code works, go read the ARM ARM.
138 pcache_type = CPU_CT_CTYPE(cpuinfo.ctr);
140 if (pcache_unified == 0) {
141 isize = CPU_CT_ISIZE(cpuinfo.ctr);
142 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
143 picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
144 if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
145 if (isize & CPU_CT_xSIZE_M)
146 picache_line_size = 0; /* not present */
150 picache_ways = multiplier <<
151 (CPU_CT_xSIZE_ASSOC(isize) - 1);
153 picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
156 dsize = CPU_CT_DSIZE(cpuinfo.ctr);
157 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
158 pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
159 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
160 if (dsize & CPU_CT_xSIZE_M)
161 pdcache_line_size = 0; /* not present */
165 pdcache_ways = multiplier <<
166 (CPU_CT_xSIZE_ASSOC(dsize) - 1);
168 pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
170 /* Print cache info. */
171 if (picache_line_size == 0 && pdcache_line_size == 0)
174 if (pcache_unified) {
175 printf(" %dKB/%dB %d-way %s unified cache\n",
177 pdcache_line_size, pdcache_ways,
178 pcache_type == 0 ? "WT" : "WB");
180 printf(" %dKB/%dB %d-way instruction cache\n",
182 picache_line_size, picache_ways);
183 printf(" %dKB/%dB %d-way %s data cache\n",
185 pdcache_line_size, pdcache_ways,
186 pcache_type == 0 ? "WT" : "WB");
191 print_v7_cache(void )
193 uint32_t type, val, size, sets, ways, linesize;
196 printf("LoUU:%d LoC:%d LoUIS:%d \n",
197 CPU_CLIDR_LOUU(cpuinfo.clidr) + 1,
198 CPU_CLIDR_LOC(cpuinfo.clidr) + 1,
199 CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1);
201 for (i = 0; i < 7; i++) {
202 type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i);
205 printf("Cache level %d:\n", i + 1);
206 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
207 type == CACHE_SEP_CACHE) {
208 cp15_csselr_set(i << 1);
209 val = cp15_ccsidr_get();
210 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
211 sets = CPUV7_CT_xSIZE_SET(val) + 1;
212 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
213 size = (ways * sets * linesize) / 1024;
215 if (type == CACHE_UNI_CACHE)
216 printf(" %dKB/%dB %d-way unified cache",
217 size, linesize,ways);
219 printf(" %dKB/%dB %d-way data cache",
220 size, linesize, ways);
221 if (val & CPUV7_CT_CTYPE_WT)
223 if (val & CPUV7_CT_CTYPE_WB)
225 if (val & CPUV7_CT_CTYPE_RA)
226 printf(" Read-Alloc");
227 if (val & CPUV7_CT_CTYPE_WA)
228 printf(" Write-Alloc");
232 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
233 cp15_csselr_set(i << 1 | 1);
234 val = cp15_ccsidr_get();
235 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
236 sets = CPUV7_CT_xSIZE_SET(val) + 1;
237 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
238 size = (ways * sets * linesize) / 1024;
239 printf(" %dKB/%dB %d-way instruction cache",
240 size, linesize, ways);
241 if (val & CPUV7_CT_CTYPE_WT)
243 if (val & CPUV7_CT_CTYPE_WB)
245 if (val & CPUV7_CT_CTYPE_RA)
246 printf(" Read-Alloc");
247 if (val & CPUV7_CT_CTYPE_WA)
248 printf(" Write-Alloc");
262 if ((hw_buf_idx + len + 2) >= 79) {
263 printf("%s,\n", hw_buf);
265 hw_buf_newline = true;
268 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, " ");
270 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", ");
271 hw_buf_newline = false;
273 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap);
277 identify_arm_cpu(void)
285 for(i = 0; i < nitems(cpu_names); i++) {
286 if (cpu_names[i].implementer == cpuinfo.implementer &&
287 cpu_names[i].part_number == cpuinfo.part_number) {
288 cpu_class = cpu_names[i].cpu_class;
289 snprintf(cpu_model, sizeof(cpu_model),
290 "%s %s r%dp%d (ECO: 0x%08X)",
291 cpu_names[i].impl_name, cpu_names[i].core_name,
292 cpuinfo.revision, cpuinfo.patch,
293 cpuinfo.midr != cpuinfo.revidr ?
295 printf("CPU: %s\n", cpu_model);
299 if (i >= nitems(cpu_names))
300 printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr);
302 printf("CPU Features: \n");
304 hw_buf_newline = true;
306 val = (cpuinfo.mpidr >> 4)& 0xF;
307 if (cpuinfo.mpidr & (1 << 31U))
308 add_cap("Multiprocessing");
309 val = (cpuinfo.id_pfr0 >> 4)& 0xF;
315 val = (cpuinfo.id_pfr1 >> 4)& 0xF;
316 if (val == 1 || val == 2)
319 val = (cpuinfo.id_pfr1 >> 12)& 0xF;
321 add_cap("Virtualization");
323 val = (cpuinfo.id_pfr1 >> 16)& 0xF;
325 add_cap("Generic Timer");
327 val = (cpuinfo.id_mmfr0 >> 0)& 0xF;
330 } else if (val >= 3) {
338 val = (cpuinfo.id_mmfr3 >> 20)& 0xF;
340 add_cap("Coherent Walk");
343 printf("%s\n", hw_buf);
345 printf("Optional instructions: \n");
347 hw_buf_newline = true;
348 val = (cpuinfo.id_isar0 >> 24)& 0xF;
350 add_cap("SDIV/UDIV (Thumb)");
352 add_cap("SDIV/UDIV");
354 val = (cpuinfo.id_isar2 >> 20)& 0xF;
355 if (val == 1 || val == 2)
358 val = (cpuinfo.id_isar2 >> 16)& 0xF;
359 if (val == 1 || val == 2 || val == 3)
362 val = (cpuinfo.id_isar2 >> 12)& 0xF;
366 val = (cpuinfo.id_isar3 >> 4)& 0xF;
370 add_cap("SIMD(ext)");
372 printf("%s\n", hw_buf);
377 if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7)