sys/arm/arm/identcpu-v6.c

   1 /*      $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1995 Mark Brinicombe.
   5  * Copyright (c) 1995 Brini.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Brini.
  19  * 4. The name of the company nor the name of the author may be used to
  20  *    endorse or promote products derived from this software without specific
  21  *    prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpu.c
  38  *
  39  * Probing and configuration for the master CPU
  40  *
  41  * Created      : 10/10/95
  42  */
  43
  44 #include <sys/cdefs.h>
  45 __FBSDID("$FreeBSD$");
  46 #include <sys/param.h>
  47 #include <sys/systm.h>
  48 #include <sys/conf.h>
  49 #include <sys/kernel.h>
  50 #include <sys/sysctl.h>
  51 #include <machine/cpu.h>
  52 #include <machine/md_var.h>
  53
  54 char machine[] = "arm";
  55
  56 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  57         machine, 0, "Machine class");
  58
  59 static char cpu_model[64];
  60 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  61     cpu_model, sizeof(cpu_model), "Machine model");
  62
  63 static char hw_buf[81];
  64 static int hw_buf_idx;
  65 static bool hw_buf_newline;
  66
  67 enum cpu_class cpu_class = CPU_CLASS_NONE;
  68
  69 static struct {
  70         int     implementer;
  71         int     part_number;
  72         char    *impl_name;
  73         char    *core_name;
  74         enum    cpu_class cpu_class;
  75 } cpu_names[] =  {
  76         {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176,    "ARM", "ARM1176",
  77             CPU_CLASS_ARM11J},
  78         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
  79             CPU_CLASS_CORTEXA},
  80         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
  81             CPU_CLASS_CORTEXA},
  82         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
  83             CPU_CLASS_CORTEXA},
  84         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
  85             CPU_CLASS_CORTEXA},
  86         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
  87             CPU_CLASS_CORTEXA},
  88         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
  89             CPU_CLASS_CORTEXA},
  90         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
  91             CPU_CLASS_CORTEXA},
  92         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
  93             CPU_CLASS_CORTEXA},
  94         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
  95             CPU_CLASS_CORTEXA},
  96         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72",
  97             CPU_CLASS_CORTEXA},
  98         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
  99             CPU_CLASS_CORTEXA},
 100
 101         {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7",
 102             CPU_CLASS_MARVELL},
 103         {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7",
 104             CPU_CLASS_MARVELL},
 105
 106         {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
 107             CPU_CLASS_KRAIT},
 108 };
 109
 110
 111 static void
 112 print_v5_cache(void)
 113 {
 114         uint32_t isize, dsize;
 115         uint32_t multiplier;
 116         int pcache_type;
 117         int pcache_unified;
 118         int picache_size;
 119         int picache_line_size;
 120         int picache_ways;
 121         int pdcache_size;
 122         int pdcache_line_size;
 123         int pdcache_ways;
 124
 125         pcache_unified = 0;
 126         picache_size = 0 ;
 127         picache_line_size = 0 ;
 128         picache_ways = 0 ;
 129         pdcache_size = 0;
 130         pdcache_line_size = 0;
 131         pdcache_ways = 0;
 132
 133         if ((cpuinfo.ctr & CPU_CT_S) == 0)
 134                 pcache_unified = 1;
 135
 136         /*
 137          * If you want to know how this code works, go read the ARM ARM.
 138          */
 139         pcache_type = CPU_CT_CTYPE(cpuinfo.ctr);
 140
 141         if (pcache_unified == 0) {
 142                 isize = CPU_CT_ISIZE(cpuinfo.ctr);
 143                 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
 144                 picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
 145                 if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
 146                         if (isize & CPU_CT_xSIZE_M)
 147                                 picache_line_size = 0; /* not present */
 148                         else
 149                                 picache_ways = 1;
 150                 } else {
 151                         picache_ways = multiplier <<
 152                             (CPU_CT_xSIZE_ASSOC(isize) - 1);
 153                 }
 154                 picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
 155         }
 156
 157         dsize = CPU_CT_DSIZE(cpuinfo.ctr);
 158         multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
 159         pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
 160         if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
 161                 if (dsize & CPU_CT_xSIZE_M)
 162                         pdcache_line_size = 0; /* not present */
 163                 else
 164                         pdcache_ways = 1;
 165         } else {
 166                 pdcache_ways = multiplier <<
 167                     (CPU_CT_xSIZE_ASSOC(dsize) - 1);
 168                 }
 169         pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
 170
 171
 172         /* Print cache info. */
 173         if (picache_line_size == 0 && pdcache_line_size == 0)
 174                 return;
 175
 176         if (pcache_unified) {
 177                 printf("  %dKB/%dB %d-way %s unified cache\n",
 178                     pdcache_size / 1024,
 179                     pdcache_line_size, pdcache_ways,
 180                     pcache_type == 0 ? "WT" : "WB");
 181         } else {
 182                 printf("  %dKB/%dB %d-way instruction cache\n",
 183                     picache_size / 1024,
 184                     picache_line_size, picache_ways);
 185                 printf("  %dKB/%dB %d-way %s data cache\n",
 186                     pdcache_size / 1024,
 187                     pdcache_line_size, pdcache_ways,
 188                     pcache_type == 0 ? "WT" : "WB");
 189         }
 190 }
 191
 192 static void
 193 print_v7_cache(void )
 194 {
 195         uint32_t type, val, size, sets, ways, linesize;
 196         int i;
 197
 198         printf("LoUU:%d LoC:%d LoUIS:%d \n",
 199             CPU_CLIDR_LOUU(cpuinfo.clidr) + 1,
 200             CPU_CLIDR_LOC(cpuinfo.clidr) + 1,
 201             CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1);
 202
 203         for (i = 0; i < 7; i++) {
 204                 type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i);
 205                 if (type == 0)
 206                         break;
 207                 printf("Cache level %d:\n", i + 1);
 208                 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
 209                     type == CACHE_SEP_CACHE) {
 210                         cp15_csselr_set(i << 1);
 211                         val = cp15_ccsidr_get();
 212                         ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
 213                         sets = CPUV7_CT_xSIZE_SET(val) + 1;
 214                         linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
 215                         size = (ways * sets * linesize) / 1024;
 216
 217                         if (type == CACHE_UNI_CACHE)
 218                                 printf(" %dKB/%dB %d-way unified cache",
 219                                     size, linesize,ways);
 220                         else
 221                                 printf(" %dKB/%dB %d-way data cache",
 222                                     size, linesize, ways);
 223                         if (val & CPUV7_CT_CTYPE_WT)
 224                                 printf(" WT");
 225                         if (val & CPUV7_CT_CTYPE_WB)
 226                                 printf(" WB");
 227                         if (val & CPUV7_CT_CTYPE_RA)
 228                                 printf(" Read-Alloc");
 229                         if (val & CPUV7_CT_CTYPE_WA)
 230                                 printf(" Write-Alloc");
 231                         printf("\n");
 232                 }
 233
 234                 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
 235                         cp15_csselr_set(i << 1 | 1);
 236                         val = cp15_ccsidr_get();
 237                         ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
 238                         sets = CPUV7_CT_xSIZE_SET(val) + 1;
 239                         linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
 240                         size = (ways * sets * linesize) / 1024;
 241                                 printf(" %dKB/%dB %d-way instruction cache",
 242                             size, linesize, ways);
 243                         if (val & CPUV7_CT_CTYPE_WT)
 244                                 printf(" WT");
 245                         if (val & CPUV7_CT_CTYPE_WB)
 246                                 printf(" WB");
 247                         if (val & CPUV7_CT_CTYPE_RA)
 248                                 printf(" Read-Alloc");
 249                         if (val & CPUV7_CT_CTYPE_WA)
 250                                 printf(" Write-Alloc");
 251                         printf("\n");
 252                 }
 253         }
 254         cp15_csselr_set(0);
 255 }
 256
 257 static void
 258 add_cap(char *cap)
 259 {
 260         int len;
 261
 262         len = strlen(cap);
 263
 264         if ((hw_buf_idx + len + 2) >= 79) {
 265                 printf("%s,\n", hw_buf);
 266                 hw_buf_idx  = 0;
 267                 hw_buf_newline = true;
 268         }
 269         if (hw_buf_newline)
 270                 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "  ");
 271         else
 272                 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", ");
 273         hw_buf_newline = false;
 274
 275
 276         hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap);
 277 }
 278
 279 void
 280 identify_arm_cpu(void)
 281 {
 282         int i;
 283         u_int val;
 284
 285         /*
 286          * CPU
 287          */
 288         for(i = 0; i < nitems(cpu_names); i++) {
 289                 if (cpu_names[i].implementer == cpuinfo.implementer &&
 290                     cpu_names[i].part_number == cpuinfo.part_number) {
 291                         cpu_class = cpu_names[i].cpu_class;
 292                         snprintf(cpu_model, sizeof(cpu_model),
 293                             "%s %s r%dp%d (ECO: 0x%08X)",
 294                             cpu_names[i].impl_name, cpu_names[i].core_name,
 295                             cpuinfo.revision, cpuinfo.patch,
 296                             cpuinfo.midr != cpuinfo.revidr ?
 297                             cpuinfo.revidr : 0);
 298                         printf("CPU: %s\n", cpu_model);
 299                         break;
 300                 }
 301
 302         }
 303         if (i >= nitems(cpu_names))
 304                 printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr);
 305
 306         printf("CPU Features: \n");
 307         hw_buf_idx = 0;
 308         hw_buf_newline = true;
 309
 310         val = (cpuinfo.mpidr >> 4)& 0xF;
 311         if (cpuinfo.mpidr & (1 << 31U))
 312                 add_cap("Multiprocessing");
 313         val = (cpuinfo.id_pfr0 >> 4)& 0xF;
 314         if (val == 1)
 315                 add_cap("Thumb");
 316         else if (val == 3)
 317                 add_cap("Thumb2");
 318
 319         val = (cpuinfo.id_pfr1 >> 4)& 0xF;
 320         if (val == 1 || val == 2)
 321                 add_cap("Security");
 322
 323         val = (cpuinfo.id_pfr1 >> 12)& 0xF;
 324         if (val == 1)
 325                 add_cap("Virtualization");
 326
 327         val = (cpuinfo.id_pfr1 >> 16)& 0xF;
 328         if (val == 1)
 329                 add_cap("Generic Timer");
 330
 331         val = (cpuinfo.id_mmfr0 >> 0)& 0xF;
 332         if (val == 2) {
 333                 add_cap("VMSAv6");
 334         } else if (val >= 3) {
 335                 add_cap("VMSAv7");
 336                 if (val >= 4)
 337                         add_cap("PXN");
 338                 if (val >= 5)
 339                         add_cap("LPAE");
 340         }
 341
 342         val = (cpuinfo.id_mmfr3 >> 20)& 0xF;
 343         if (val == 1)
 344                 add_cap("Coherent Walk");
 345
 346         if (hw_buf_idx != 0)
 347                 printf("%s\n", hw_buf);
 348
 349         printf("Optional instructions: \n");
 350         hw_buf_idx = 0;
 351         hw_buf_newline = true;
 352         val = (cpuinfo.id_isar0 >> 24)& 0xF;
 353         if (val == 1)
 354                 add_cap("SDIV/UDIV (Thumb)");
 355         else if (val == 2)
 356                 add_cap("SDIV/UDIV");
 357
 358         val = (cpuinfo.id_isar2 >> 20)& 0xF;
 359         if (val == 1 || val == 2)
 360                 add_cap("UMULL");
 361
 362         val = (cpuinfo.id_isar2 >> 16)& 0xF;
 363         if (val == 1 || val == 2 || val == 3)
 364                 add_cap("SMULL");
 365
 366         val = (cpuinfo.id_isar2 >> 12)& 0xF;
 367         if (val == 1)
 368                 add_cap("MLA");
 369
 370         val = (cpuinfo.id_isar3 >> 4)& 0xF;
 371         if (val == 1)
 372                 add_cap("SIMD");
 373         else if (val == 3)
 374                 add_cap("SIMD(ext)");
 375         if (hw_buf_idx != 0)
 376                 printf("%s\n", hw_buf);
 377
 378         /*
 379          * Cache
 380          */
 381         if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7)
 382                 print_v7_cache();
 383         else
 384                 print_v5_cache();
 385 }