sys/arm/arm/identcpu-v6.c

   1 /*      $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1995 Mark Brinicombe.
   5  * Copyright (c) 1995 Brini.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Brini.
  19  * 4. The name of the company nor the name of the author may be used to
  20  *    endorse or promote products derived from this software without specific
  21  *    prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpu.c
  38  *
  39  * Probing and configuration for the master CPU
  40  *
  41  * Created      : 10/10/95
  42  */
  43
  44 #include <sys/cdefs.h>
  45 __FBSDID("$FreeBSD$");
  46 #include <sys/param.h>
  47 #include <sys/systm.h>
  48 #include <sys/conf.h>
  49 #include <sys/kernel.h>
  50 #include <sys/sysctl.h>
  51 #include <machine/cpu.h>
  52 #include <machine/md_var.h>
  53
  54 char machine[] = "arm";
  55
  56 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  57         machine, 0, "Machine class");
  58
  59 static char hw_buf[81];
  60 static int hw_buf_idx;
  61 static bool hw_buf_newline;
  62
  63 enum cpu_class cpu_class = CPU_CLASS_NONE;
  64
  65 static struct {
  66         int     implementer;
  67         int     part_number;
  68         char    *impl_name;
  69         char    *core_name;
  70         enum    cpu_class cpu_class;
  71 } cpu_names[] =  {
  72         {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176,    "ARM", "ARM1176",
  73             CPU_CLASS_ARM11J},
  74         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
  75             CPU_CLASS_CORTEXA},
  76         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
  77             CPU_CLASS_CORTEXA},
  78         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
  79             CPU_CLASS_CORTEXA},
  80         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
  81             CPU_CLASS_CORTEXA},
  82         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
  83             CPU_CLASS_CORTEXA},
  84         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
  85             CPU_CLASS_CORTEXA},
  86         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
  87             CPU_CLASS_CORTEXA},
  88         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
  89             CPU_CLASS_CORTEXA},
  90         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
  91             CPU_CLASS_CORTEXA},
  92         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72",
  93             CPU_CLASS_CORTEXA},
  94         {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
  95             CPU_CLASS_CORTEXA},
  96
  97         {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7",
  98             CPU_CLASS_MARVELL},
  99         {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7",
 100             CPU_CLASS_MARVELL},
 101
 102         {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
 103             CPU_CLASS_KRAIT},
 104 };
 105
 106
 107 static void
 108 print_v5_cache(void)
 109 {
 110         uint32_t isize, dsize;
 111         uint32_t multiplier;
 112         int pcache_type;
 113         int pcache_unified;
 114         int picache_size;
 115         int picache_line_size;
 116         int picache_ways;
 117         int pdcache_size;
 118         int pdcache_line_size;
 119         int pdcache_ways;
 120
 121         pcache_unified = 0;
 122         picache_size = 0 ;
 123         picache_line_size = 0 ;
 124         picache_ways = 0 ;
 125         pdcache_size = 0;
 126         pdcache_line_size = 0;
 127         pdcache_ways = 0;
 128
 129         if ((cpuinfo.ctr & CPU_CT_S) == 0)
 130                 pcache_unified = 1;
 131
 132         /*
 133          * If you want to know how this code works, go read the ARM ARM.
 134          */
 135         pcache_type = CPU_CT_CTYPE(cpuinfo.ctr);
 136
 137         if (pcache_unified == 0) {
 138                 isize = CPU_CT_ISIZE(cpuinfo.ctr);
 139                 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
 140                 picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
 141                 if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
 142                         if (isize & CPU_CT_xSIZE_M)
 143                                 picache_line_size = 0; /* not present */
 144                         else
 145                                 picache_ways = 1;
 146                 } else {
 147                         picache_ways = multiplier <<
 148                             (CPU_CT_xSIZE_ASSOC(isize) - 1);
 149                 }
 150                 picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
 151         }
 152
 153         dsize = CPU_CT_DSIZE(cpuinfo.ctr);
 154         multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
 155         pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
 156         if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
 157                 if (dsize & CPU_CT_xSIZE_M)
 158                         pdcache_line_size = 0; /* not present */
 159                 else
 160                         pdcache_ways = 1;
 161         } else {
 162                 pdcache_ways = multiplier <<
 163                     (CPU_CT_xSIZE_ASSOC(dsize) - 1);
 164                 }
 165         pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
 166
 167
 168         /* Print cache info. */
 169         if (picache_line_size == 0 && pdcache_line_size == 0)
 170                 return;
 171
 172         if (pcache_unified) {
 173                 printf("  %dKB/%dB %d-way %s unified cache\n",
 174                     pdcache_size / 1024,
 175                     pdcache_line_size, pdcache_ways,
 176                     pcache_type == 0 ? "WT" : "WB");
 177         } else {
 178                 printf("  %dKB/%dB %d-way instruction cache\n",
 179                     picache_size / 1024,
 180                     picache_line_size, picache_ways);
 181                 printf("  %dKB/%dB %d-way %s data cache\n",
 182                     pdcache_size / 1024,
 183                     pdcache_line_size, pdcache_ways,
 184                     pcache_type == 0 ? "WT" : "WB");
 185         }
 186 }
 187
 188 static void
 189 print_v7_cache(void )
 190 {
 191         uint32_t type, val, size, sets, ways, linesize;
 192         int i;
 193
 194         printf("LoUU:%d LoC:%d LoUIS:%d \n",
 195             CPU_CLIDR_LOUU(cpuinfo.clidr) + 1,
 196             CPU_CLIDR_LOC(cpuinfo.clidr) + 1,
 197             CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1);
 198
 199         for (i = 0; i < 7; i++) {
 200                 type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i);
 201                 if (type == 0)
 202                         break;
 203                 printf("Cache level %d:\n", i + 1);
 204                 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
 205                     type == CACHE_SEP_CACHE) {
 206                         cp15_csselr_set(i << 1);
 207                         val = cp15_ccsidr_get();
 208                         ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
 209                         sets = CPUV7_CT_xSIZE_SET(val) + 1;
 210                         linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
 211                         size = (ways * sets * linesize) / 1024;
 212
 213                         if (type == CACHE_UNI_CACHE)
 214                                 printf(" %dKB/%dB %d-way unified cache",
 215                                     size, linesize,ways);
 216                         else
 217                                 printf(" %dKB/%dB %d-way data cache",
 218                                     size, linesize, ways);
 219                         if (val & CPUV7_CT_CTYPE_WT)
 220                                 printf(" WT");
 221                         if (val & CPUV7_CT_CTYPE_WB)
 222                                 printf(" WB");
 223                                 if (val & CPUV7_CT_CTYPE_RA)
 224                                 printf(" Read-Alloc");
 225                         if (val & CPUV7_CT_CTYPE_WA)
 226                                 printf(" Write-Alloc");
 227                         printf("\n");
 228                 }
 229
 230                 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
 231                         cp15_csselr_set(i << 1 | 1);
 232                         val = cp15_ccsidr_get();
 233                         ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
 234                         sets = CPUV7_CT_xSIZE_SET(val) + 1;
 235                         linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
 236                         size = (ways * sets * linesize) / 1024;
 237                                 printf(" %dKB/%dB %d-way instruction cache",
 238                             size, linesize, ways);
 239                         if (val & CPUV7_CT_CTYPE_WT)
 240                                 printf(" WT");
 241                         if (val & CPUV7_CT_CTYPE_WB)
 242                                 printf(" WB");
 243                         if (val & CPUV7_CT_CTYPE_RA)
 244                                 printf(" Read-Alloc");
 245                         if (val & CPUV7_CT_CTYPE_WA)
 246                                 printf(" Write-Alloc");
 247                         printf("\n");
 248                 }
 249         }
 250         cp15_csselr_set(0);
 251 }
 252
 253 static void
 254 add_cap(char *cap)
 255 {
 256         int len;
 257
 258         len = strlen(cap);
 259
 260         if ((hw_buf_idx + len + 2) >= 79) {
 261                 printf("%s,\n", hw_buf);
 262                 hw_buf_idx  = 0;
 263                 hw_buf_newline = true;
 264         }
 265         if (hw_buf_newline)
 266                 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "  ");
 267         else
 268                 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", ");
 269         hw_buf_newline = false;
 270
 271
 272         hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap);
 273 }
 274
 275 void
 276 identify_arm_cpu(void)
 277 {
 278         int i;
 279         u_int val;
 280
 281         /*
 282          * CPU
 283          */
 284         for(i = 0; i < nitems(cpu_names); i++) {
 285                 if (cpu_names[i].implementer == cpuinfo.implementer &&
 286                     cpu_names[i].part_number == cpuinfo.part_number) {
 287                         cpu_class = cpu_names[i].cpu_class;
 288                         printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n",
 289                             cpu_names[i].impl_name, cpu_names[i].core_name,
 290                             cpuinfo.revision, cpuinfo.patch,
 291                             cpuinfo.midr != cpuinfo.revidr ?
 292                             cpuinfo.revidr : 0);
 293                         break;
 294                 }
 295
 296         }
 297         if (i >= nitems(cpu_names))
 298                 printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr);
 299
 300         printf("CPU Features: \n");
 301         hw_buf_idx = 0;
 302         hw_buf_newline = true;
 303
 304         val = (cpuinfo.mpidr >> 4)& 0xF;
 305         if (cpuinfo.mpidr & (1 << 31U))
 306                 add_cap("Multiprocessing");
 307         val = (cpuinfo.id_pfr0 >> 4)& 0xF;
 308         if (val == 1)
 309                 add_cap("Thumb");
 310         else if (val == 3)
 311                 add_cap("Thumb2");
 312
 313         val = (cpuinfo.id_pfr1 >> 4)& 0xF;
 314         if (val == 1 || val == 2)
 315                 add_cap("Security");
 316
 317         val = (cpuinfo.id_pfr1 >> 12)& 0xF;
 318         if (val == 1)
 319                 add_cap("Virtualization");
 320
 321         val = (cpuinfo.id_pfr1 >> 16)& 0xF;
 322         if (val == 1)
 323                 add_cap("Generic Timer");
 324
 325         val = (cpuinfo.id_mmfr0 >> 0)& 0xF;
 326         if (val == 2) {
 327                 add_cap("VMSAv6");
 328         } else if (val >= 3) {
 329                 add_cap("VMSAv7");
 330                 if (val >= 4)
 331                         add_cap("PXN");
 332                 if (val >= 5)
 333                         add_cap("LPAE");
 334         }
 335
 336         val = (cpuinfo.id_mmfr3 >> 20)& 0xF;
 337         if (val == 1)
 338                 add_cap("Coherent Walk");
 339
 340         if (hw_buf_idx != 0)
 341                 printf("%s\n", hw_buf);
 342
 343         printf("Optional instructions: \n");
 344         hw_buf_idx = 0;
 345         hw_buf_newline = true;
 346         val = (cpuinfo.id_isar0 >> 24)& 0xF;
 347         if (val == 1)
 348                 add_cap("SDIV/UDIV (Thumb)");
 349         else if (val == 2)
 350                 add_cap("SDIV/UDIV");
 351
 352         val = (cpuinfo.id_isar2 >> 20)& 0xF;
 353         if (val == 1 || val == 2)
 354                 add_cap("UMULL");
 355
 356         val = (cpuinfo.id_isar2 >> 16)& 0xF;
 357         if (val == 1 || val == 2 || val == 3)
 358                 add_cap("SMULL");
 359
 360         val = (cpuinfo.id_isar2 >> 12)& 0xF;
 361         if (val == 1)
 362                 add_cap("MLA");
 363
 364         val = (cpuinfo.id_isar3 >> 4)& 0xF;
 365         if (val == 1)
 366                 add_cap("SIMD");
 367         else if (val == 3)
 368                 add_cap("SIMD(ext)");
 369         if (hw_buf_idx != 0)
 370                 printf("%s\n", hw_buf);
 371
 372         /*
 373          * Cache
 374          */
 375         if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7)
 376                 print_v7_cache();
 377         else
 378                 print_v5_cache();
 379 }