sys/arm/arm/identcpu.c

   1 /*      $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1995 Mark Brinicombe.
   5  * Copyright (c) 1995 Brini.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Brini.
  19  * 4. The name of the company nor the name of the author may be used to
  20  *    endorse or promote products derived from this software without specific
  21  *    prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpu.c
  38  *
  39  * Probing and configuration for the master CPU
  40  *
  41  * Created      : 10/10/95
  42  */
  43
  44 #include <sys/cdefs.h>
  45 __FBSDID("$FreeBSD$");
  46 #include <sys/systm.h>
  47 #include <sys/param.h>
  48 #include <sys/malloc.h>
  49 #include <sys/time.h>
  50 #include <sys/proc.h>
  51 #include <sys/conf.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <machine/cpu.h>
  55
  56 #include <machine/cpuconf.h>
  57
  58 char machine[] = "arm";
  59
  60 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  61         machine, 0, "Machine class");
  62 enum cpu_class {
  63         CPU_CLASS_NONE,
  64         CPU_CLASS_ARM2,
  65         CPU_CLASS_ARM2AS,
  66         CPU_CLASS_ARM3,
  67         CPU_CLASS_ARM6,
  68         CPU_CLASS_ARM7,
  69         CPU_CLASS_ARM7TDMI,
  70         CPU_CLASS_ARM8,
  71         CPU_CLASS_ARM9TDMI,
  72         CPU_CLASS_ARM9ES,
  73         CPU_CLASS_ARM9EJS,
  74         CPU_CLASS_ARM10E,
  75         CPU_CLASS_ARM10EJ,
  76         CPU_CLASS_SA1,
  77         CPU_CLASS_XSCALE,
  78         CPU_CLASS_ARM11J,
  79         CPU_CLASS_MARVELL
  80 };
  81
  82 static const char * const generic_steppings[16] = {
  83         "rev 0",        "rev 1",        "rev 2",        "rev 3",
  84         "rev 4",        "rev 5",        "rev 6",        "rev 7",
  85         "rev 8",        "rev 9",        "rev 10",       "rev 11",
  86         "rev 12",       "rev 13",       "rev 14",       "rev 15",
  87 };
  88
  89 static const char * const sa110_steppings[16] = {
  90         "rev 0",        "step J",       "step K",       "step S",
  91         "step T",       "rev 5",        "rev 6",        "rev 7",
  92         "rev 8",        "rev 9",        "rev 10",       "rev 11",
  93         "rev 12",       "rev 13",       "rev 14",       "rev 15",
  94 };
  95
  96 static const char * const sa1100_steppings[16] = {
  97         "rev 0",        "step B",       "step C",       "rev 3",
  98         "rev 4",        "rev 5",        "rev 6",        "rev 7",
  99         "step D",       "step E",       "rev 10"        "step G",
 100         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 101 };
 102
 103 static const char * const sa1110_steppings[16] = {
 104         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 105         "step B-0",     "step B-1",     "step B-2",     "step B-3",
 106         "step B-4",     "step B-5",     "rev 10",       "rev 11",
 107         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 108 };
 109
 110 static const char * const ixp12x0_steppings[16] = {
 111         "(IXP1200 step A)",             "(IXP1200 step B)",
 112         "rev 2",                        "(IXP1200 step C)",
 113         "(IXP1200 step D)",             "(IXP1240/1250 step A)",
 114         "(IXP1240 step B)",             "(IXP1250 step B)",
 115         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 116         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 117 };
 118
 119 static const char * const xscale_steppings[16] = {
 120         "step A-0",     "step A-1",     "step B-0",     "step C-0",
 121         "step D-0",     "rev 5",        "rev 6",        "rev 7",
 122         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 123         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 124 };
 125
 126 static const char * const i80219_steppings[16] = {
 127         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 128         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 129         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 130         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 131 };
 132
 133 static const char * const i80321_steppings[16] = {
 134         "step A-0",     "step B-0",     "rev 2",        "rev 3",
 135         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 136         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 137         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 138 };
 139
 140 static const char * const i81342_steppings[16] = {
 141         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 142         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 143         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 144         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 145 };
 146
 147 /* Steppings for PXA2[15]0 */
 148 static const char * const pxa2x0_steppings[16] = {
 149         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 150         "step B-2",     "step C-0",     "rev 6",        "rev 7",
 151         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 152         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 153 };
 154
 155 /* Steppings for PXA255/26x.
 156  * rev 5: PXA26x B0, rev 6: PXA255 A0
 157  */
 158 static const char * const pxa255_steppings[16] = {
 159         "rev 0",        "rev 1",        "rev 2",        "step A-0",
 160         "rev 4",        "step B-0",     "step A-0",     "rev 7",
 161         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 162         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 163 };
 164
 165 /* Stepping for PXA27x */
 166 static const char * const pxa27x_steppings[16] = {
 167         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 168         "step C-0",     "rev 5",        "rev 6",        "rev 7",
 169         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 170         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 171 };
 172
 173 static const char * const ixp425_steppings[16] = {
 174         "step 0 (A0)",  "rev 1 (ARMv5TE)", "rev 2",     "rev 3",
 175         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 176         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 177         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 178 };
 179
 180 struct cpuidtab {
 181         u_int32_t       cpuid;
 182         enum            cpu_class cpu_class;
 183         const char      *cpu_name;
 184         const char * const *cpu_steppings;
 185 };
 186
 187 const struct cpuidtab cpuids[] = {
 188         { CPU_ID_ARM2,          CPU_CLASS_ARM2,         "ARM2",
 189           generic_steppings },
 190         { CPU_ID_ARM250,        CPU_CLASS_ARM2AS,       "ARM250",
 191           generic_steppings },
 192
 193         { CPU_ID_ARM3,          CPU_CLASS_ARM3,         "ARM3",
 194           generic_steppings },
 195
 196         { CPU_ID_ARM600,        CPU_CLASS_ARM6,         "ARM600",
 197           generic_steppings },
 198         { CPU_ID_ARM610,        CPU_CLASS_ARM6,         "ARM610",
 199           generic_steppings },
 200         { CPU_ID_ARM620,        CPU_CLASS_ARM6,         "ARM620",
 201           generic_steppings },
 202
 203         { CPU_ID_ARM700,        CPU_CLASS_ARM7,         "ARM700",
 204           generic_steppings },
 205         { CPU_ID_ARM710,        CPU_CLASS_ARM7,         "ARM710",
 206           generic_steppings },
 207         { CPU_ID_ARM7500,       CPU_CLASS_ARM7,         "ARM7500",
 208           generic_steppings },
 209         { CPU_ID_ARM710A,       CPU_CLASS_ARM7,         "ARM710a",
 210           generic_steppings },
 211         { CPU_ID_ARM7500FE,     CPU_CLASS_ARM7,         "ARM7500FE",
 212           generic_steppings },
 213         { CPU_ID_ARM710T,       CPU_CLASS_ARM7TDMI,     "ARM710T",
 214           generic_steppings },
 215         { CPU_ID_ARM720T,       CPU_CLASS_ARM7TDMI,     "ARM720T",
 216           generic_steppings },
 217         { CPU_ID_ARM740T8K,     CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
 218           generic_steppings },
 219         { CPU_ID_ARM740T4K,     CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
 220           generic_steppings },
 221
 222         { CPU_ID_ARM810,        CPU_CLASS_ARM8,         "ARM810",
 223           generic_steppings },
 224
 225         { CPU_ID_ARM920T,       CPU_CLASS_ARM9TDMI,     "ARM920T",
 226           generic_steppings },
 227         { CPU_ID_ARM920T_ALT,   CPU_CLASS_ARM9TDMI,     "ARM920T",
 228           generic_steppings },
 229         { CPU_ID_ARM922T,       CPU_CLASS_ARM9TDMI,     "ARM922T",
 230           generic_steppings },
 231         { CPU_ID_ARM926EJS,     CPU_CLASS_ARM9EJS,      "ARM926EJ-S",
 232           generic_steppings },
 233         { CPU_ID_ARM940T,       CPU_CLASS_ARM9TDMI,     "ARM940T",
 234           generic_steppings },
 235         { CPU_ID_ARM946ES,      CPU_CLASS_ARM9ES,       "ARM946E-S",
 236           generic_steppings },
 237         { CPU_ID_ARM966ES,      CPU_CLASS_ARM9ES,       "ARM966E-S",
 238           generic_steppings },
 239         { CPU_ID_ARM966ESR1,    CPU_CLASS_ARM9ES,       "ARM966E-S",
 240           generic_steppings },
 241         { CPU_ID_TI925T,        CPU_CLASS_ARM9TDMI,     "TI ARM925T",
 242           generic_steppings },
 243
 244         { CPU_ID_ARM1020E,      CPU_CLASS_ARM10E,       "ARM1020E",
 245           generic_steppings },
 246         { CPU_ID_ARM1022ES,     CPU_CLASS_ARM10E,       "ARM1022E-S",
 247           generic_steppings },
 248         { CPU_ID_ARM1026EJS,    CPU_CLASS_ARM10EJ,      "ARM1026EJ-S",
 249           generic_steppings },
 250
 251         { CPU_ID_SA110,         CPU_CLASS_SA1,          "SA-110",
 252           sa110_steppings },
 253         { CPU_ID_SA1100,        CPU_CLASS_SA1,          "SA-1100",
 254           sa1100_steppings },
 255         { CPU_ID_SA1110,        CPU_CLASS_SA1,          "SA-1110",
 256           sa1110_steppings },
 257
 258         { CPU_ID_IXP1200,       CPU_CLASS_SA1,          "IXP1200",
 259           ixp12x0_steppings },
 260
 261         { CPU_ID_80200,         CPU_CLASS_XSCALE,       "i80200",
 262           xscale_steppings },
 263
 264         { CPU_ID_80321_400,     CPU_CLASS_XSCALE,       "i80321 400MHz",
 265           i80321_steppings },
 266         { CPU_ID_80321_600,     CPU_CLASS_XSCALE,       "i80321 600MHz",
 267           i80321_steppings },
 268         { CPU_ID_80321_400_B0,  CPU_CLASS_XSCALE,       "i80321 400MHz",
 269           i80321_steppings },
 270         { CPU_ID_80321_600_B0,  CPU_CLASS_XSCALE,       "i80321 600MHz",
 271           i80321_steppings },
 272
 273         { CPU_ID_81342,         CPU_CLASS_XSCALE,       "i81342",
 274           i81342_steppings },
 275
 276         { CPU_ID_80219_400,     CPU_CLASS_XSCALE,       "i80219 400MHz",
 277           i80219_steppings },
 278         { CPU_ID_80219_600,     CPU_CLASS_XSCALE,       "i80219 600MHz",
 279           i80219_steppings },
 280
 281         { CPU_ID_PXA27X,        CPU_CLASS_XSCALE,       "PXA27x",
 282           pxa27x_steppings },
 283         { CPU_ID_PXA250A,       CPU_CLASS_XSCALE,       "PXA250",
 284           pxa2x0_steppings },
 285         { CPU_ID_PXA210A,       CPU_CLASS_XSCALE,       "PXA210",
 286           pxa2x0_steppings },
 287         { CPU_ID_PXA250B,       CPU_CLASS_XSCALE,       "PXA250",
 288           pxa2x0_steppings },
 289         { CPU_ID_PXA210B,       CPU_CLASS_XSCALE,       "PXA210",
 290           pxa2x0_steppings },
 291         { CPU_ID_PXA250C,       CPU_CLASS_XSCALE,       "PXA255",
 292           pxa255_steppings },
 293         { CPU_ID_PXA210C,       CPU_CLASS_XSCALE,       "PXA210",
 294           pxa2x0_steppings },
 295
 296         { CPU_ID_IXP425_533,    CPU_CLASS_XSCALE,       "IXP425 533MHz",
 297           ixp425_steppings },
 298         { CPU_ID_IXP425_400,    CPU_CLASS_XSCALE,       "IXP425 400MHz",
 299           ixp425_steppings },
 300         { CPU_ID_IXP425_266,    CPU_CLASS_XSCALE,       "IXP425 266MHz",
 301           ixp425_steppings },
 302
 303         { CPU_ID_ARM1136JS,     CPU_CLASS_ARM11J,       "ARM1136J-S",
 304           generic_steppings },
 305         { CPU_ID_ARM1136JSR1,   CPU_CLASS_ARM11J,       "ARM1136J-S R1",
 306           generic_steppings },
 307
 308         { CPU_ID_MV88FR131,     CPU_CLASS_MARVELL,      "Feroceon 88FR131",
 309           generic_steppings },
 310
 311         { CPU_ID_MV88FR571_VD,  CPU_CLASS_MARVELL,      "Feroceon 88FR571-VD",
 312           generic_steppings },
 313
 314         { CPU_ID_MV88FR571_41,  CPU_CLASS_MARVELL,      "Early Feroceon 88FR571",
 315           generic_steppings },
 316
 317         { 0, CPU_CLASS_NONE, NULL, NULL }
 318 };
 319
 320 struct cpu_classtab {
 321         const char      *class_name;
 322         const char      *class_option;
 323 };
 324
 325 const struct cpu_classtab cpu_classes[] = {
 326         { "unknown",    NULL },                 /* CPU_CLASS_NONE */
 327         { "ARM2",       "CPU_ARM2" },           /* CPU_CLASS_ARM2 */
 328         { "ARM2as",     "CPU_ARM250" },         /* CPU_CLASS_ARM2AS */
 329         { "ARM3",       "CPU_ARM3" },           /* CPU_CLASS_ARM3 */
 330         { "ARM6",       "CPU_ARM6" },           /* CPU_CLASS_ARM6 */
 331         { "ARM7",       "CPU_ARM7" },           /* CPU_CLASS_ARM7 */
 332         { "ARM7TDMI",   "CPU_ARM7TDMI" },       /* CPU_CLASS_ARM7TDMI */
 333         { "ARM8",       "CPU_ARM8" },           /* CPU_CLASS_ARM8 */
 334         { "ARM9TDMI",   "CPU_ARM9TDMI" },       /* CPU_CLASS_ARM9TDMI */
 335         { "ARM9E-S",    "CPU_ARM9E" },          /* CPU_CLASS_ARM9ES */
 336         { "ARM9EJ-S",   "CPU_ARM9E" },          /* CPU_CLASS_ARM9EJS */
 337         { "ARM10E",     "CPU_ARM10" },          /* CPU_CLASS_ARM10E */
 338         { "ARM10EJ",    "CPU_ARM10" },          /* CPU_CLASS_ARM10EJ */
 339         { "SA-1",       "CPU_SA110" },          /* CPU_CLASS_SA1 */
 340         { "XScale",     "CPU_XSCALE_..." },     /* CPU_CLASS_XSCALE */
 341         { "ARM11J",     "CPU_ARM11" },          /* CPU_CLASS_ARM11J */
 342 };
 343
 344 /*
 345  * Report the type of the specified arm processor. This uses the generic and
 346  * arm specific information in the cpu structure to identify the processor.
 347  * The remaining fields in the cpu structure are filled in appropriately.
 348  */
 349
 350 static const char * const wtnames[] = {
 351         "write-through",
 352         "write-back",
 353         "write-back",
 354         "**unknown 3**",
 355         "**unknown 4**",
 356         "write-back-locking",           /* XXX XScale-specific? */
 357         "write-back-locking-A",
 358         "write-back-locking-B",
 359         "**unknown 8**",
 360         "**unknown 9**",
 361         "**unknown 10**",
 362         "**unknown 11**",
 363         "**unknown 12**",
 364         "**unknown 13**",
 365         "write-back-locking-C",
 366         "**unknown 15**",
 367 };
 368
 369
 370 extern int ctrl;
 371 void
 372 identify_arm_cpu(void)
 373 {
 374         u_int cpuid;
 375         enum cpu_class cpu_class = CPU_CLASS_NONE;
 376         int i;
 377
 378         cpuid = cpu_id();
 379
 380         if (cpuid == 0) {
 381                 printf("Processor failed probe - no CPU ID\n");
 382                 return;
 383         }
 384
 385         for (i = 0; cpuids[i].cpuid != 0; i++)
 386                 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
 387                         cpu_class = cpuids[i].cpu_class;
 388                         printf("CPU: %s %s (%s core)\n",
 389                             cpuids[i].cpu_name,
 390                             cpuids[i].cpu_steppings[cpuid &
 391                             CPU_ID_REVISION_MASK],
 392                             cpu_classes[cpu_class].class_name);
 393                         break;
 394                 }
 395         if (cpuids[i].cpuid == 0)
 396                 printf("unknown CPU (ID = 0x%x)\n", cpuid);
 397
 398         printf(" ");
 399         switch (cpu_class) {
 400         case CPU_CLASS_ARM6:
 401         case CPU_CLASS_ARM7:
 402         case CPU_CLASS_ARM7TDMI:
 403         case CPU_CLASS_ARM8:
 404                 if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
 405                         printf(" IDC disabled");
 406                 else
 407                         printf(" IDC enabled");
 408                 break;
 409         case CPU_CLASS_ARM9TDMI:
 410         case CPU_CLASS_ARM9ES:
 411         case CPU_CLASS_ARM9EJS:
 412         case CPU_CLASS_ARM10E:
 413         case CPU_CLASS_ARM10EJ:
 414         case CPU_CLASS_SA1:
 415         case CPU_CLASS_XSCALE:
 416         case CPU_CLASS_ARM11J:
 417                 if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0)
 418                         printf(" DC disabled");
 419                 else
 420                         printf(" DC enabled");
 421                 if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0)
 422                         printf(" IC disabled");
 423                 else
 424                         printf(" IC enabled");
 425 #ifdef CPU_XSCALE_81342
 426                 if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0)
 427                         printf(" L2 disabled");
 428                 else
 429                         printf(" L2 enabled");
 430 #endif
 431                 break;
 432         default:
 433                 break;
 434         }
 435         if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
 436                 printf(" WB disabled");
 437         else
 438                 printf(" WB enabled");
 439
 440         if (ctrl & CPU_CONTROL_LABT_ENABLE)
 441                 printf(" LABT");
 442         else
 443                 printf(" EABT");
 444
 445         if (ctrl & CPU_CONTROL_BPRD_ENABLE)
 446                 printf(" branch prediction enabled");
 447
 448         printf("\n");
 449         /* Print cache info. */
 450         if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
 451                 return;
 452
 453         if (arm_pcache_unified) {
 454                 printf("  %dKB/%dB %d-way %s unified cache\n",
 455                     arm_pdcache_size / 1024,
 456                     arm_pdcache_line_size, arm_pdcache_ways,
 457                     wtnames[arm_pcache_type]);
 458         } else {
 459                 printf("  %dKB/%dB %d-way Instruction cache\n",
 460                     arm_picache_size / 1024,
 461                     arm_picache_line_size, arm_picache_ways);
 462                 printf("  %dKB/%dB %d-way %s Data cache\n",
 463                     arm_pdcache_size / 1024,
 464                     arm_pdcache_line_size, arm_pdcache_ways,
 465                     wtnames[arm_pcache_type]);
 466         }
 467 }
 468