1 /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */
4 * Copyright (c) 1995 Mark Brinicombe.
5 * Copyright (c) 1995 Brini.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Probing and configuration for the master CPU
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
46 #include <sys/systm.h>
47 #include <sys/param.h>
48 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <machine/cpu.h>
56 #include <machine/cpuconf.h>
58 char machine[] = "arm";
60 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
61 machine, 0, "Machine class");
78 static const char * const generic_steppings[16] = {
79 "rev 0", "rev 1", "rev 2", "rev 3",
80 "rev 4", "rev 5", "rev 6", "rev 7",
81 "rev 8", "rev 9", "rev 10", "rev 11",
82 "rev 12", "rev 13", "rev 14", "rev 15",
85 static const char * const sa110_steppings[16] = {
86 "rev 0", "step J", "step K", "step S",
87 "step T", "rev 5", "rev 6", "rev 7",
88 "rev 8", "rev 9", "rev 10", "rev 11",
89 "rev 12", "rev 13", "rev 14", "rev 15",
92 static const char * const sa1100_steppings[16] = {
93 "rev 0", "step B", "step C", "rev 3",
94 "rev 4", "rev 5", "rev 6", "rev 7",
95 "step D", "step E", "rev 10" "step G",
96 "rev 12", "rev 13", "rev 14", "rev 15",
99 static const char * const sa1110_steppings[16] = {
100 "step A-0", "rev 1", "rev 2", "rev 3",
101 "step B-0", "step B-1", "step B-2", "step B-3",
102 "step B-4", "step B-5", "rev 10", "rev 11",
103 "rev 12", "rev 13", "rev 14", "rev 15",
106 static const char * const ixp12x0_steppings[16] = {
107 "(IXP1200 step A)", "(IXP1200 step B)",
108 "rev 2", "(IXP1200 step C)",
109 "(IXP1200 step D)", "(IXP1240/1250 step A)",
110 "(IXP1240 step B)", "(IXP1250 step B)",
111 "rev 8", "rev 9", "rev 10", "rev 11",
112 "rev 12", "rev 13", "rev 14", "rev 15",
115 static const char * const xscale_steppings[16] = {
116 "step A-0", "step A-1", "step B-0", "step C-0",
117 "step D-0", "rev 5", "rev 6", "rev 7",
118 "rev 8", "rev 9", "rev 10", "rev 11",
119 "rev 12", "rev 13", "rev 14", "rev 15",
122 static const char * const i80321_steppings[16] = {
123 "step A-0", "step B-0", "rev 2", "rev 3",
124 "rev 4", "rev 5", "rev 6", "rev 7",
125 "rev 8", "rev 9", "rev 10", "rev 11",
126 "rev 12", "rev 13", "rev 14", "rev 15",
129 static const char * const pxa2x0_steppings[16] = {
130 "step A-0", "step A-1", "step B-0", "step B-1",
131 "step B-2", "step C-0", "rev 6", "rev 7",
132 "rev 8", "rev 9", "rev 10", "rev 11",
133 "rev 12", "rev 13", "rev 14", "rev 15",
136 static const char * const ixp425_steppings[16] = {
137 "step 0", "rev 1", "rev 2", "rev 3",
138 "rev 4", "rev 5", "rev 6", "rev 7",
139 "rev 8", "rev 9", "rev 10", "rev 11",
140 "rev 12", "rev 13", "rev 14", "rev 15",
145 enum cpu_class cpu_class;
146 const char *cpu_name;
147 const char * const *cpu_steppings;
150 const struct cpuidtab cpuids[] = {
151 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2",
153 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250",
156 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3",
159 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600",
161 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610",
163 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620",
166 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700",
168 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710",
170 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500",
172 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a",
174 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE",
176 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T",
178 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T",
180 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
182 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
185 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
188 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
190 { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T",
192 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
194 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T",
196 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S",
198 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S",
200 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
202 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
205 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
207 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
210 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
212 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
214 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
217 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
220 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200",
223 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz",
225 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz",
227 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz",
229 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz",
232 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250",
234 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210",
236 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250",
238 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210",
240 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA250",
242 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
245 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz",
247 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz",
249 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
252 { 0, CPU_CLASS_NONE, NULL, NULL }
255 struct cpu_classtab {
256 const char *class_name;
257 const char *class_option;
260 const struct cpu_classtab cpu_classes[] = {
261 { "unknown", NULL }, /* CPU_CLASS_NONE */
262 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */
263 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */
264 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */
265 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */
266 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */
267 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */
268 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
269 { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */
270 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */
271 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
272 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */
273 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
277 * Report the type of the specified arm processor. This uses the generic and
278 * arm specific information in the cpu structure to identify the processor.
279 * The remaining fields in the cpu structure are filled in appropriately.
282 static const char * const wtnames[] = {
288 "write-back-locking", /* XXX XScale-specific? */
289 "write-back-locking-A",
290 "write-back-locking-B",
301 void setPQL2(int *const size, int *const ways);
304 setPQL2(int *const size, int *const ways)
312 identify_arm_cpu(void)
315 enum cpu_class cpu_class = CPU_CLASS_NONE;
321 printf("Processor failed probe - no CPU ID\n");
325 for (i = 0; cpuids[i].cpuid != 0; i++)
326 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
327 cpu_class = cpuids[i].cpu_class;
328 printf("CPU: %s %s (%s core)\n",
330 cpuids[i].cpu_steppings[cpuid &
331 CPU_ID_REVISION_MASK],
332 cpu_classes[cpu_class].class_name);
335 if (cpuids[i].cpuid == 0)
336 printf("unknown CPU (ID = 0x%x)\n", cpuid);
342 case CPU_CLASS_ARM7TDMI:
344 if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
345 printf(" IDC disabled");
347 printf(" IDC enabled");
349 case CPU_CLASS_ARM9TDMI:
350 case CPU_CLASS_ARM10E:
352 case CPU_CLASS_XSCALE:
353 if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0)
354 printf(" DC disabled");
356 printf(" DC enabled");
357 if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0)
358 printf(" IC disabled");
360 printf(" IC enabled");
365 if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
366 printf(" WB disabled");
368 printf(" WB enabled");
370 if (ctrl & CPU_CONTROL_LABT_ENABLE)
375 if (ctrl & CPU_CONTROL_BPRD_ENABLE)
376 printf(" branch prediction enabled");
379 /* Print cache info. */
380 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
383 if (arm_pcache_unified) {
384 printf(" %dKB/%dB %d-way %s unified cache\n",
385 arm_pdcache_size / 1024,
386 arm_pdcache_line_size, arm_pdcache_ways,
387 wtnames[arm_pcache_type]);
389 printf(" %dKB/%dB %d-way Instruction cache\n",
390 arm_picache_size / 1024,
391 arm_picache_line_size, arm_picache_ways);
392 printf(" %dKB/%dB %d-way %s Data cache\n",
393 arm_pdcache_size / 1024,
394 arm_pdcache_line_size, arm_pdcache_ways,
395 wtnames[arm_pcache_type]);