1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright 2011 Semihalf
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/syscall.h>
38 #include <machine/asm.h>
39 #include <machine/armreg.h>
40 #include <machine/cpuconf.h>
41 #include <machine/pte-v4.h>
43 __FBSDID("$FreeBSD$");
45 /* 2K initial stack is plenty, it is only used by initarm() */
46 #define INIT_ARM_STACK_SIZE 2048
48 #define CPWAIT_BRANCH \
52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
53 mov tmp, tmp /* wait for it to complete */ ;\
54 CPWAIT_BRANCH /* branch to next insn */
57 * This is for libkvm, and should be the address of the beginning
58 * of the kernel text segment (not necessarily the same as kernbase).
60 * These are being phased out. Newer copies of libkvm don't need these
61 * values as the information is added to the core file by inspecting
68 .set kernbase,KERNBASE
70 .set physaddr,PHYSADDR
74 * On entry for FreeBSD boot ABI:
75 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
76 * r1 - if (r0 == 0) then metadata pointer
77 * On entry for Linux boot ABI:
79 * r1 - machine type (passed as arg2 to initarm)
80 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
82 * For both types of boot we gather up the args, put them in a struct arm_boot_params
83 * structure and pass that to initarm.
88 STOP_UNWINDING /* Can't unwind into the bootloader! */
90 mov r9, r0 /* 0 or boot mode from boot2 */
91 mov r8, r1 /* Save Machine type */
92 mov ip, r2 /* Save meta data */
93 mov fp, r3 /* Future expansion */
95 /* Make sure interrupts are disabled. */
97 orr r7, r7, #(PSR_I | PSR_F)
100 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
102 * Sanity check the configuration.
103 * FLASHADDR and LOADERRAMADDR depend on PHYSADDR in some cases.
104 * ARMv4 and ARMv5 make assumptions on where they are loaded.
105 * TODO: Fix the ARMv4/v5 case.
108 #error PHYSADDR must be defined for this configuration
111 /* Check if we're running from flash. */
114 * If we're running with MMU disabled, test against the
115 * physical address instead.
118 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
120 ldrne r6, =LOADERRAMADDR
142 Lram_offset: .word from_ram-_C_LABEL(_start)
148 /* Disable MMU for a while */
150 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
151 CPU_CONTROL_WBUF_ENABLE)
152 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
153 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
163 * Build page table from scratch.
167 * Figure out the physical address we're loaded at by assuming this
168 * entry point code is in the first L1 section and so if we clear the
169 * offset bits of the pc that will give us the section-aligned load
170 * address, which remains in r5 throughout all the following code.
172 ldr r2, =(L1_S_OFFSET)
175 /* Find the delta between VA and PA, result stays in r0 throughout. */
177 bl translate_va_to_pa
180 * First map the entire 4GB address space as VA=PA. It's mapped as
181 * normal (cached) memory because it's for things like accessing the
182 * parameters passed in from the bootloader, which might be at any
183 * physical address, different for every platform.
191 * Next we do 64MiB starting at the physical load address, mapped to
192 * the VA the kernel is linked for.
195 ldr r2, =(KERNVIRTADDR)
198 #if defined(PHYSADDR) && (KERNVIRTADDR != KERNBASE)
200 * If the kernel wasn't loaded at the beginning of the ram, map the memory
201 * before the kernel too, as some ports use that for pagetables, stack, etc...
205 ldr r3, =((KERNVIRTADDR - KERNBASE) / L1_S_SIZE)
209 /* Create a device mapping for early_printf if specified. */
210 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
214 bl build_device_pagetables
217 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
218 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
220 /* Set the Domain Access register. Very important! */
221 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
222 mcr p15, 0, r0, c3, c0, 0
227 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
234 /* Transition the PC from physical to virtual addressing. */
240 ldmia r1, {r1, r2, sp} /* Set initial stack and */
241 sub r2, r2, r1 /* get zero init data */
244 str r3, [r1], #0x0004 /* get zero init data */
249 mov r1, #28 /* loader info size is 28 bytes also second arg */
250 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
251 mov r0, sp /* loader info pointer is first arg */
252 bic sp, sp, #7 /* align stack to 8 bytes */
253 str r1, [r0] /* Store length of loader info */
254 str r9, [r0, #4] /* Store r0 from boot loader */
255 str r8, [r0, #8] /* Store r1 from boot loader */
256 str ip, [r0, #12] /* store r2 from boot loader */
257 str fp, [r0, #16] /* store r3 from boot loader */
258 str r5, [r0, #20] /* store the physical address */
259 adr r4, Lpagetable /* load the pagetable address */
261 str r5, [r0, #24] /* store the pagetable address */
262 mov fp, #0 /* trace back starts here */
263 bl _C_LABEL(initarm) /* Off we go */
265 /* init arm will return the new stack pointer. */
268 bl _C_LABEL(mi_startup) /* call mi_startup()! */
270 adr r0, .Lmainreturned
275 #define VA_TO_PA_POINTER(name, table) \
281 * Returns the physical address of a magic va to pa pointer.
282 * r0 - The pagetable data pointer. This must be built using the
283 * VA_TO_PA_POINTER macro.
285 * VA_TO_PA_POINTER(Lpagetable, pagetable)
288 * bl translate_va_to_pa
289 * r0 will now contain the physical address of pagetable
295 /* At this point: r2 = VA - PA */
298 * Find the physical address of the table. After these two
302 * r0 = va(pagetable) - (VA - PA)
303 * = va(pagetable) - VA + PA
311 * Builds the page table
312 * r0 - The table base address
313 * r1 - The physical address (trashed)
314 * r2 - The virtual address (trashed)
315 * r3 - The number of 1MiB sections
318 * Addresses must be 1MiB aligned
320 build_device_pagetables:
321 ldr r4, =(L1_TYPE_S|L1_S_AP(AP_KRW))
324 /* Set the required page attributed */
325 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
329 /* Move the virtual address to the correct bit location */
330 lsr r2, #(L1_S_SHIFT - 2)
336 add r1, r1, #(L1_S_SIZE)
342 VA_TO_PA_POINTER(Lpagetable, pagetable)
352 .word svcstk + INIT_ARM_STACK_SIZE
358 .asciz "main() returned"
363 .space INIT_ARM_STACK_SIZE
366 * Memory for the initial pagetable. We are unable to place this in
367 * the bss as this will be cleared after the table is loaded.
369 .section ".init_pagetable"
370 .align 14 /* 16KiB aligned */
378 .word _C_LABEL(cpufuncs)
382 bic r2, r2, #(PSR_MODE)
383 orr r2, r2, #(PSR_SVC32_MODE)
384 orr r2, r2, #(PSR_I | PSR_F)
387 ldr r4, .Lcpu_reset_address
392 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
394 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
397 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
401 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
407 * MMU & IDC off, 32 bit program & data space
408 * Hurl ourselves into the ROM
410 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
412 mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
416 * _cpu_reset_address contains the address to branch to, to complete
417 * the cpu reset after turning the MMU off
418 * This variable is provided by the hardware specific code
421 .word _C_LABEL(cpu_reset_address)
424 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
425 * v4 MMU disable instruction needs executing... it is an illegal instruction
426 * on f.e. ARM6/7 that locks up the computer in an endless illegal
427 * instruction / data-abort / reset loop.
429 .Lcpu_reset_needs_v4_MMU_disable:
430 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
450 .global _C_LABEL(esym)
451 _C_LABEL(esym): .word _C_LABEL(end)
462 * Call the sigreturn system call.
464 * We have to load r7 manually rather than using
465 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
466 * correct. Using the alternative places esigcode at the address
467 * of the data rather than the address one past the data.
470 ldr r7, [pc, #12] /* Load SYS_sigreturn */
473 /* Well if that failed we better exit quick ! */
475 ldr r7, [pc, #8] /* Load SYS_exit */
478 /* Branch back to retry SYS_sigreturn */
485 .global _C_LABEL(esigcode)
491 .long esigcode-sigcode
493 /* End of locore.S */