2 * Copyright 2004-2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2012-2014 Ian Lepore <ian@FreeBSD.org>
4 * Copyright 2013-2014 Andrew Turner <andrew@FreeBSD.org>
5 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
6 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/syscall.h>
33 #include <machine/acle-compat.h>
34 #include <machine/asm.h>
35 #include <machine/asmacros.h>
36 #include <machine/armreg.h>
37 #include <machine/sysreg.h>
38 #include <machine/cpuconf.h>
39 #include <machine/pte-v6.h>
41 __FBSDID("$FreeBSD$");
45 #if defined(__ARM_ARCH_7VE__) || defined(__clang__)
47 * HYP support is in bintuils >= 2.21 and gcc >= 4.9 defines __ARM_ARCH_7VE__
48 * when enabled. llvm >= 3.6 supports it too.
51 #define MSR_ELR_HYP(regnum) msr elr_hyp, lr
54 #define MSR_ELR_HYP(regnum) .word (0xe12ef300 | regnum)
55 #define ERET .word 0xe160006e
57 #endif /* __ARM_ARCH >= 7 */
59 /* A small statically-allocated stack used only during initarm() and AP startup. */
60 #define INIT_ARM_STACK_SIZE 2048
67 /* Leave HYP mode */ ;\
69 and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */ ;\
70 teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */ ;\
72 /* Ensure that IRQ, FIQ and Aborts will be disabled after eret */ ;\
74 bic r0, r0, #(PSR_MODE) ;\
75 orr r0, r0, #(PSR_SVC32_MODE) ;\
76 orr r0, r0, #(PSR_I | PSR_F | PSR_A) ;\
78 /* Exit hypervisor mode */ ;\
85 #endif /* __ARM_ARCH >= 7 */
88 * On entry for FreeBSD boot ABI:
89 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
90 * r1 - if (r0 == 0) then metadata pointer
91 * On entry for Linux boot ABI:
93 * r1 - machine type (passed as arg2 to initarm)
94 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
96 * For both types of boot we gather up the args, put them in a struct arm_boot_params
97 * structure and pass that to initarm.
102 STOP_UNWINDING /* Can't unwind into the bootloader! */
104 /* Make sure interrupts are disabled. */
107 mov r8, r0 /* 0 or boot mode from boot2 */
108 mov r9, r1 /* Save Machine type */
109 mov r10, r2 /* Save meta data */
110 mov r11, r3 /* Future expansion */
115 * Check whether data cache is enabled. If it is, then we know
116 * current tags are valid (not power-on garbage values) and there
117 * might be dirty lines that need cleaning. Disable cache to prevent
118 * new lines being allocated, then call wbinv_poc_all to clean it.
121 tst r7, #CPU_CONTROL_DC_ENABLE
122 blne dcache_wbinv_poc_all
124 /* ! Do not write to memory between wbinv and disabling cache ! */
127 * Now there are no dirty lines, but there may still be lines marked
128 * valid. Disable all caches and the MMU, and invalidate everything
129 * before setting up new page tables and re-enabling the mmu.
132 bic r7, #CPU_CONTROL_DC_ENABLE
133 bic r7, #CPU_CONTROL_MMU_ENABLE
134 bic r7, #CPU_CONTROL_IC_ENABLE
135 bic r7, #CPU_CONTROL_BPRD_ENABLE
136 bic r7, #CPU_CONTROL_SW_ENABLE
137 orr r7, #CPU_CONTROL_UNAL_ENABLE
138 orr r7, #CPU_CONTROL_AFLT_ENABLE
139 orr r7, #CPU_CONTROL_VECRELOC
143 bl dcache_inv_poc_all
149 * Build page table from scratch.
153 * Figure out the physical address we're loaded at by assuming this
154 * entry point code is in the first L1 section and so if we clear the
155 * offset bits of the pc that will give us the section-aligned load
156 * address, which remains in r5 throughout all the following code.
158 ldr r2, =(L1_S_OFFSET)
161 /* Find the delta between VA and PA, result stays in r0 throughout. */
163 bl translate_va_to_pa
166 * First map the entire 4GB address space as VA=PA. It's mapped as
167 * normal (cached) memory because it's for things like accessing the
168 * parameters passed in from the bootloader, which might be at any
169 * physical address, different for every platform.
177 * Next we do 64MiB starting at the physical load address, mapped to
178 * the VA the kernel is linked for.
181 ldr r2, =(KERNVIRTADDR)
185 /* Create a device mapping for early_printf if specified. */
186 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
190 bl build_device_pagetables
194 /* Transition the PC from physical to virtual addressing. */
198 /* Setup stack, clear BSS */
200 ldmia r1, {r1, r2, sp} /* Set initial stack and */
201 add sp, sp, #INIT_ARM_STACK_SIZE
202 sub r2, r2, r1 /* get zero init data */
205 str r3, [r1], #0x0004 /* get zero init data */
209 mov r1, #28 /* loader info size is 28 bytes also second arg */
210 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
211 mov r0, sp /* loader info pointer is first arg */
212 bic sp, sp, #7 /* align stack to 8 bytes */
213 str r1, [r0] /* Store length of loader info */
214 str r8, [r0, #4] /* Store r0 from boot loader */
215 str r9, [r0, #8] /* Store r1 from boot loader */
216 str r10, [r0, #12] /* store r2 from boot loader */
217 str r11, [r0, #16] /* store r3 from boot loader */
218 str r5, [r0, #20] /* store the physical address */
219 adr r4, Lpagetable /* load the pagetable address */
221 str r5, [r0, #24] /* store the pagetable address */
222 mov fp, #0 /* trace back starts here */
223 bl _C_LABEL(initarm) /* Off we go */
225 /* init arm will return the new stack pointer. */
228 bl _C_LABEL(mi_startup) /* call mi_startup()! */
230 ldr r0, =.Lmainreturned
235 #define VA_TO_PA_POINTER(name, table) \
241 * Returns the physical address of a magic va to pa pointer.
242 * r0 - The pagetable data pointer. This must be built using the
243 * VA_TO_PA_POINTER macro.
245 * VA_TO_PA_POINTER(Lpagetable, pagetable)
248 * bl translate_va_to_pa
249 * r0 will now contain the physical address of pagetable
255 /* At this point: r2 = VA - PA */
258 * Find the physical address of the table. After these two
262 * r0 = va(pagetable) - (VA - PA)
263 * = va(pagetable) - VA + PA
272 * r0 - the table base address
277 /* Setup TLB and MMU registers */
278 mcr CP15_TTBR0(r0) /* Set TTB */
280 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */
282 /* Set the Domain Access register */
283 mov r0, #DOMAIN_CLIENT /* Only domain #0 is used */
287 * Set TEX remap registers
288 * - All is set to uncacheable memory
294 mcr CP15_TLBIALL /* Flush TLB */
300 orr r0, r0, #CPU_CONTROL_MMU_ENABLE
301 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
302 orr r0, r0, #CPU_CONTROL_TR_ENABLE
303 orr r0, r0, #CPU_CONTROL_AF_ENABLE
307 mcr CP15_TLBIALL /* Flush TLB */
308 mcr CP15_BPIALL /* Flush Branch predictor */
317 * Init SMP coherent mode, enable caching and switch to final MMU table.
318 * Called with disabled caches
319 * r0 - The table base address
320 * r1 - clear bits for aux register
321 * r2 - set bits for aux register
323 ASENTRY_NP(reinit_mmu)
329 /* !! Be very paranoid here !! */
330 /* !! We cannot write single bit here !! */
332 #if 0 /* XXX writeback shouldn't be necessary */
333 /* Write back and invalidate all integrated caches */
334 bl dcache_wbinv_poc_all
336 bl dcache_inv_pou_all
342 /* Set auxiliary register */
344 bic r8, r7, r5 /* Mask bits */
345 eor r8, r8, r6 /* Set bits */
353 orr r7, #CPU_CONTROL_DC_ENABLE
354 orr r7, #CPU_CONTROL_IC_ENABLE
355 orr r7, #CPU_CONTROL_BPRD_ENABLE
359 mcr CP15_TTBR0(r4) /* Set new TTB */
363 mcr CP15_TLBIALL /* Flush TLB */
364 mcr CP15_BPIALL /* Flush Branch predictor */
368 #if 0 /* XXX writeback shouldn't be necessary */
369 /* Write back and invalidate all integrated caches */
370 bl dcache_wbinv_poc_all
372 bl dcache_inv_pou_all
383 * Builds the page table
384 * r0 - The table base address
385 * r1 - The physical address (trashed)
386 * r2 - The virtual address (trashed)
387 * r3 - The number of 1MiB sections
390 * Addresses must be 1MiB aligned
392 build_device_pagetables:
393 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
396 /* Set the required page attributed */
397 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
401 /* Move the virtual address to the correct bit location */
402 lsr r2, #(PTE1_SHIFT - 2)
408 add r1, r1, #(PTE1_SIZE)
414 VA_TO_PA_POINTER(Lpagetable, boot_pt1)
418 .word _edata /* Note that these three items are */
419 .word _ebss /* loaded with a single ldmia and */
420 .word svcstk /* must remain in order together. */
423 .asciz "main() returned"
428 .space INIT_ARM_STACK_SIZE * MAXCPU
431 * Memory for the initial pagetable. We are unable to place this in
432 * the bss as this will be cleared after the table is loaded.
434 .section ".init_pagetable"
435 .align 14 /* 16KiB aligned */
444 .word _C_LABEL(cpufuncs)
449 /* Make sure interrupts are disabled. */
454 /* Setup core, disable all caches. */
456 bic r0, #CPU_CONTROL_MMU_ENABLE
457 bic r0, #CPU_CONTROL_DC_ENABLE
458 bic r0, #CPU_CONTROL_IC_ENABLE
459 bic r0, #CPU_CONTROL_BPRD_ENABLE
460 bic r0, #CPU_CONTROL_SW_ENABLE
461 orr r0, #CPU_CONTROL_UNAL_ENABLE
462 orr r0, #CPU_CONTROL_AFLT_ENABLE
463 orr r0, #CPU_CONTROL_VECRELOC
468 /* Invalidate L1 cache I+D cache */
469 bl dcache_inv_pou_all
474 /* Find the delta between VA and PA */
476 bl translate_va_to_pa
480 adr r1, .Lstart+8 /* Get initstack pointer from */
481 ldr sp, [r1] /* startup data. */
482 mrc CP15_MPIDR(r0) /* Get processor id number. */
484 mov r1, #INIT_ARM_STACK_SIZE
485 mul r2, r1, r0 /* Point sp to initstack */
486 add sp, sp, r2 /* area for this processor. */
488 /* Switch to virtual addresses. */
491 mov fp, #0 /* trace back starts here */
492 bl _C_LABEL(init_secondary)/* Off we go, cpu id in r0. */
500 .asciz "init_secondary() returned"
506 /* XXX re-implement !!! */
508 bl dcache_wbinv_poc_all
510 ldr r4, .Lcpu_reset_address
519 * _cpu_reset_address contains the address to branch to, to complete
520 * the cpu reset after turning the MMU off
521 * This variable is provided by the hardware specific code
524 .word _C_LABEL(cpu_reset_address)
544 .global _C_LABEL(esym)
545 _C_LABEL(esym): .word _C_LABEL(end)
556 * Call the sigreturn system call.
558 * We have to load r7 manually rather than using
559 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
560 * correct. Using the alternative places esigcode at the address
561 * of the data rather than the address one past the data.
564 ldr r7, [pc, #12] /* Load SYS_sigreturn */
567 /* Well if that failed we better exit quick ! */
569 ldr r7, [pc, #8] /* Load SYS_exit */
572 /* Branch back to retry SYS_sigreturn */
579 .global _C_LABEL(esigcode)
585 .long esigcode-sigcode
587 /* End of locore.S */