2 * Copyright 2004-2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2012-2014 Ian Lepore <ian@FreeBSD.org>
4 * Copyright 2013-2014 Andrew Turner <andrew@FreeBSD.org>
5 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
6 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/syscall.h>
33 #include <machine/asm.h>
34 #include <machine/asmacros.h>
35 #include <machine/armreg.h>
36 #include <machine/sysreg.h>
37 #include <machine/pte-v6.h>
39 __FBSDID("$FreeBSD$");
41 /* We map 64MB of kernel unless overridden in assym.inc by the kernel option. */
43 #define LOCORE_MAP_MB 64
47 #if defined(__ARM_ARCH_7VE__) || defined(__clang__)
49 * HYP support is in bintuils >= 2.21 and gcc >= 4.9 defines __ARM_ARCH_7VE__
50 * when enabled. llvm >= 3.6 supports it too.
54 #endif /* __ARM_ARCH >= 7 */
56 /* A small statically-allocated stack used only during initarm() and AP startup. */
57 #define INIT_ARM_STACK_SIZE 2048
64 /* Leave HYP mode */ ;\
66 and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */ ;\
67 teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */ ;\
69 /* Install Hypervisor Stub Exception Vector */ ;\
70 bl hypervisor_stub_vect_install ;\
72 adr r1, hypmode_enabled ;\
74 /* Ensure that IRQ, FIQ and Aborts will be disabled after eret */ ;\
76 bic r0, r0, #(PSR_MODE) ;\
77 orr r0, r0, #(PSR_SVC32_MODE) ;\
78 orr r0, r0, #(PSR_I | PSR_F | PSR_A) ;\
80 /* Exit hypervisor mode */ ;\
86 adr r1, hypmode_enabled ;\
91 #endif /* __ARM_ARCH >= 7 */
94 * On entry for FreeBSD boot ABI:
95 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
96 * r1 - if (r0 == 0) then metadata pointer
97 * On entry for Linux boot ABI:
99 * r1 - machine type (passed as arg2 to initarm)
100 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
102 * For both types of boot we gather up the args, put them in a struct arm_boot_params
103 * structure and pass that to initarm.
108 STOP_UNWINDING /* Can't unwind into the bootloader! */
110 /* Make sure interrupts are disabled. */
113 mov r8, r0 /* 0 or boot mode from boot2 */
114 mov r9, r1 /* Save Machine type */
115 mov r10, r2 /* Save meta data */
116 mov r11, r3 /* Future expansion */
118 # If HYP-MODE is active, install an exception vector stub
122 * Check whether data cache is enabled. If it is, then we know
123 * current tags are valid (not power-on garbage values) and there
124 * might be dirty lines that need cleaning. Disable cache to prevent
125 * new lines being allocated, then call wbinv_poc_all to clean it.
128 tst r7, #CPU_CONTROL_DC_ENABLE
129 blne dcache_wbinv_poc_all
131 /* ! Do not write to memory between wbinv and disabling cache ! */
134 * Now there are no dirty lines, but there may still be lines marked
135 * valid. Disable all caches and the MMU, and invalidate everything
136 * before setting up new page tables and re-enabling the mmu.
139 bic r7, #CPU_CONTROL_DC_ENABLE
140 bic r7, #CPU_CONTROL_AFLT_ENABLE
141 bic r7, #CPU_CONTROL_MMU_ENABLE
142 bic r7, #CPU_CONTROL_IC_ENABLE
143 bic r7, #CPU_CONTROL_BPRD_ENABLE
144 bic r7, #CPU_CONTROL_SW_ENABLE
145 orr r7, #CPU_CONTROL_UNAL_ENABLE
146 orr r7, #CPU_CONTROL_VECRELOC
150 bl dcache_inv_poc_all
156 * Build page table from scratch.
160 * Figure out the physical address we're loaded at by assuming this
161 * entry point code is in the first L1 section and so if we clear the
162 * offset bits of the pc that will give us the section-aligned load
163 * address, which remains in r5 throughout all the following code.
165 ldr r2, =(L1_S_OFFSET)
168 /* Find the delta between VA and PA, result stays in r0 throughout. */
170 bl translate_va_to_pa
173 * First map the entire 4GB address space as VA=PA. It's mapped as
174 * normal (cached) memory because it's for things like accessing the
175 * parameters passed in from the bootloader, which might be at any
176 * physical address, different for every platform.
184 * Next we map the kernel starting at the physical load address, mapped
185 * to the VA the kernel is linked for. The default size we map is 64MiB
186 * but it can be overridden with a kernel option.
189 ldr r2, =(KERNVIRTADDR)
190 ldr r3, =(LOCORE_MAP_MB)
193 /* Create a device mapping for early_printf if specified. */
194 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
198 bl build_device_pagetables
202 /* Transition the PC from physical to virtual addressing. */
206 /* Setup stack, clear BSS */
208 ldmia r1, {r1, r2, sp} /* Set initial stack and */
209 add sp, sp, #INIT_ARM_STACK_SIZE
210 sub r2, r2, r1 /* get zero init data */
213 str r3, [r1], #0x0004 /* get zero init data */
217 mov r1, #28 /* loader info size is 28 bytes also second arg */
218 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
219 mov r0, sp /* loader info pointer is first arg */
220 bic sp, sp, #7 /* align stack to 8 bytes */
221 str r1, [r0] /* Store length of loader info */
222 str r8, [r0, #4] /* Store r0 from boot loader */
223 str r9, [r0, #8] /* Store r1 from boot loader */
224 str r10, [r0, #12] /* store r2 from boot loader */
225 str r11, [r0, #16] /* store r3 from boot loader */
226 str r5, [r0, #20] /* store the physical address */
227 adr r4, Lpagetable /* load the pagetable address */
229 str r5, [r0, #24] /* store the pagetable address */
230 mov fp, #0 /* trace back starts here */
231 bl _C_LABEL(initarm) /* Off we go */
233 /* init arm will return the new stack pointer. */
236 bl _C_LABEL(mi_startup) /* call mi_startup()! */
238 ldr r0, =.Lmainreturned
243 #define VA_TO_PA_POINTER(name, table) \
249 * Returns the physical address of a magic va to pa pointer.
250 * r0 - The pagetable data pointer. This must be built using the
251 * VA_TO_PA_POINTER macro.
253 * VA_TO_PA_POINTER(Lpagetable, pagetable)
256 * bl translate_va_to_pa
257 * r0 will now contain the physical address of pagetable
263 /* At this point: r2 = VA - PA */
266 * Find the physical address of the table. After these two
270 * r0 = va(pagetable) - (VA - PA)
271 * = va(pagetable) - VA + PA
280 * r0 - the table base address
285 /* Setup TLB and MMU registers */
286 mcr CP15_TTBR0(r0) /* Set TTB */
288 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */
290 /* Set the Domain Access register */
291 mov r0, #DOMAIN_CLIENT /* Only domain #0 is used */
295 * Set TEX remap registers
296 * - All is set to uncacheable memory
302 mcr CP15_TLBIALL /* Flush TLB */
308 orr r0, r0, #CPU_CONTROL_MMU_ENABLE
309 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
310 orr r0, r0, #CPU_CONTROL_TR_ENABLE
311 orr r0, r0, #CPU_CONTROL_AF_ENABLE
315 mcr CP15_TLBIALL /* Flush TLB */
316 mcr CP15_BPIALL /* Flush Branch predictor */
325 * Init SMP coherent mode, enable caching and switch to final MMU table.
326 * Called with disabled caches
327 * r0 - The table base address
328 * r1 - clear bits for aux register
329 * r2 - set bits for aux register
331 ASENTRY_NP(reinit_mmu)
337 /* !! Be very paranoid here !! */
338 /* !! We cannot write single bit here !! */
340 #if 0 /* XXX writeback shouldn't be necessary */
341 /* Write back and invalidate all integrated caches */
342 bl dcache_wbinv_poc_all
344 bl dcache_inv_pou_all
350 /* Set auxiliary register */
352 bic r8, r7, r5 /* Mask bits */
353 eor r8, r8, r6 /* Set bits */
361 orr r7, #CPU_CONTROL_DC_ENABLE
362 orr r7, #CPU_CONTROL_IC_ENABLE
363 orr r7, #CPU_CONTROL_BPRD_ENABLE
367 mcr CP15_TTBR0(r4) /* Set new TTB */
371 mcr CP15_TLBIALL /* Flush TLB */
372 mcr CP15_BPIALL /* Flush Branch predictor */
376 #if 0 /* XXX writeback shouldn't be necessary */
377 /* Write back and invalidate all integrated caches */
378 bl dcache_wbinv_poc_all
380 bl dcache_inv_pou_all
391 * Builds the page table
392 * r0 - The table base address
393 * r1 - The physical address (trashed)
394 * r2 - The virtual address (trashed)
395 * r3 - The number of 1MiB sections
398 * Addresses must be 1MiB aligned
400 build_device_pagetables:
401 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
404 /* Set the required page attributed */
405 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
409 /* Move the virtual address to the correct bit location */
410 lsr r2, #(PTE1_SHIFT - 2)
416 add r1, r1, #(PTE1_SIZE)
422 VA_TO_PA_POINTER(Lpagetable, boot_pt1)
424 .global _C_LABEL(hypmode_enabled)
425 _C_LABEL(hypmode_enabled):
429 .word _edata /* Note that these three items are */
430 .word _ebss /* loaded with a single ldmia and */
431 .word svcstk /* must remain in order together. */
434 .asciz "main() returned"
439 .space INIT_ARM_STACK_SIZE * MAXCPU
442 * Memory for the initial pagetable. We are unable to place this in
443 * the bss as this will be cleared after the table is loaded.
445 .section ".init_pagetable", "aw", %nobits
446 .align 14 /* 16KiB aligned */
457 /* Make sure interrupts are disabled. */
462 /* Setup core, disable all caches. */
464 bic r0, #CPU_CONTROL_MMU_ENABLE
465 bic r0, #CPU_CONTROL_AFLT_ENABLE
466 bic r0, #CPU_CONTROL_DC_ENABLE
467 bic r0, #CPU_CONTROL_IC_ENABLE
468 bic r0, #CPU_CONTROL_BPRD_ENABLE
469 bic r0, #CPU_CONTROL_SW_ENABLE
470 orr r0, #CPU_CONTROL_UNAL_ENABLE
471 orr r0, #CPU_CONTROL_VECRELOC
476 /* Invalidate L1 cache I+D cache */
477 bl dcache_inv_pou_all
482 /* Find the delta between VA and PA */
484 bl translate_va_to_pa
488 adr r1, .Lstart+8 /* Get initstack pointer from */
489 ldr sp, [r1] /* startup data. */
490 mrc CP15_MPIDR(r0) /* Get processor id number. */
492 mov r1, #INIT_ARM_STACK_SIZE
493 mul r2, r1, r0 /* Point sp to initstack */
494 add sp, sp, r2 /* area for this processor. */
496 /* Switch to virtual addresses. */
499 mov fp, #0 /* trace back starts here */
500 bl _C_LABEL(init_secondary)/* Off we go, cpu id in r0. */
508 .asciz "init_secondary() returned"
514 /* XXX re-implement !!! */
516 bl dcache_wbinv_poc_all
518 ldr r4, .Lcpu_reset_address
527 * _cpu_reset_address contains the address to branch to, to complete
528 * the cpu reset after turning the MMU off
529 * This variable is provided by the hardware specific code
532 .word _C_LABEL(cpu_reset_address)
552 .global _C_LABEL(esym)
553 _C_LABEL(esym): .word _C_LABEL(end)
564 * Call the sigreturn system call.
566 * We have to load r7 manually rather than using
567 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
568 * correct. Using the alternative places esigcode at the address
569 * of the data rather than the address one past the data.
572 ldr r7, [pc, #12] /* Load SYS_sigreturn */
575 /* Well if that failed we better exit quick ! */
577 ldr r7, [pc, #8] /* Load SYS_exit */
580 /* Branch back to retry SYS_sigreturn */
587 .global _C_LABEL(esigcode)
593 .long esigcode-sigcode
595 /* End of locore.S */