2 * Copyright 2004-2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2012-2014 Ian Lepore <ian@FreeBSD.org>
4 * Copyright 2013-2014 Andrew Turner <andrew@FreeBSD.org>
5 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
6 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/syscall.h>
33 #include <machine/asm.h>
34 #include <machine/asmacros.h>
35 #include <machine/armreg.h>
36 #include <machine/sysreg.h>
37 #include <machine/pte-v6.h>
39 __FBSDID("$FreeBSD$");
42 #if defined(__ARM_ARCH_7VE__) || defined(__clang__)
44 * HYP support is in bintuils >= 2.21 and gcc >= 4.9 defines __ARM_ARCH_7VE__
45 * when enabled. llvm >= 3.6 supports it too.
49 #endif /* __ARM_ARCH >= 7 */
51 /* A small statically-allocated stack used only during initarm() and AP startup. */
52 #define INIT_ARM_STACK_SIZE 2048
59 /* Leave HYP mode */ ;\
61 and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */ ;\
62 teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */ ;\
64 /* Install Hypervisor Stub Exception Vector */ ;\
65 bl hypervisor_stub_vect_install ;\
67 adr r1, hypmode_enabled ;\
69 /* Ensure that IRQ, FIQ and Aborts will be disabled after eret */ ;\
71 bic r0, r0, #(PSR_MODE) ;\
72 orr r0, r0, #(PSR_SVC32_MODE) ;\
73 orr r0, r0, #(PSR_I | PSR_F | PSR_A) ;\
75 /* Exit hypervisor mode */ ;\
81 adr r1, hypmode_enabled ;\
86 #endif /* __ARM_ARCH >= 7 */
89 * On entry for FreeBSD boot ABI:
90 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
91 * r1 - if (r0 == 0) then metadata pointer
92 * On entry for Linux boot ABI:
94 * r1 - machine type (passed as arg2 to initarm)
95 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
97 * For both types of boot we gather up the args, put them in a struct arm_boot_params
98 * structure and pass that to initarm.
103 STOP_UNWINDING /* Can't unwind into the bootloader! */
105 /* Make sure interrupts are disabled. */
108 mov r8, r0 /* 0 or boot mode from boot2 */
109 mov r9, r1 /* Save Machine type */
110 mov r10, r2 /* Save meta data */
111 mov r11, r3 /* Future expansion */
113 # If HYP-MODE is active, install an exception vector stub
117 * Check whether data cache is enabled. If it is, then we know
118 * current tags are valid (not power-on garbage values) and there
119 * might be dirty lines that need cleaning. Disable cache to prevent
120 * new lines being allocated, then call wbinv_poc_all to clean it.
123 tst r7, #CPU_CONTROL_DC_ENABLE
124 blne dcache_wbinv_poc_all
126 /* ! Do not write to memory between wbinv and disabling cache ! */
129 * Now there are no dirty lines, but there may still be lines marked
130 * valid. Disable all caches and the MMU, and invalidate everything
131 * before setting up new page tables and re-enabling the mmu.
134 bic r7, #CPU_CONTROL_DC_ENABLE
135 bic r7, #CPU_CONTROL_AFLT_ENABLE
136 bic r7, #CPU_CONTROL_MMU_ENABLE
137 bic r7, #CPU_CONTROL_IC_ENABLE
138 bic r7, #CPU_CONTROL_BPRD_ENABLE
139 bic r7, #CPU_CONTROL_SW_ENABLE
140 orr r7, #CPU_CONTROL_UNAL_ENABLE
141 orr r7, #CPU_CONTROL_VECRELOC
145 bl dcache_inv_poc_all
151 * Build page table from scratch.
155 * Figure out the physical address we're loaded at by assuming this
156 * entry point code is in the first L1 section and so if we clear the
157 * offset bits of the pc that will give us the section-aligned load
158 * address, which remains in r5 throughout all the following code.
160 ldr r2, =(L1_S_OFFSET)
163 /* Find the delta between VA and PA, result stays in r0 throughout. */
165 bl translate_va_to_pa
168 * First map the entire 4GB address space as VA=PA. It's mapped as
169 * normal (cached) memory because it's for things like accessing the
170 * parameters passed in from the bootloader, which might be at any
171 * physical address, different for every platform.
179 * Next we do 64MiB starting at the physical load address, mapped to
180 * the VA the kernel is linked for.
183 ldr r2, =(KERNVIRTADDR)
187 /* Create a device mapping for early_printf if specified. */
188 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
192 bl build_device_pagetables
196 /* Transition the PC from physical to virtual addressing. */
200 /* Setup stack, clear BSS */
202 ldmia r1, {r1, r2, sp} /* Set initial stack and */
203 add sp, sp, #INIT_ARM_STACK_SIZE
204 sub r2, r2, r1 /* get zero init data */
207 str r3, [r1], #0x0004 /* get zero init data */
211 mov r1, #28 /* loader info size is 28 bytes also second arg */
212 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
213 mov r0, sp /* loader info pointer is first arg */
214 bic sp, sp, #7 /* align stack to 8 bytes */
215 str r1, [r0] /* Store length of loader info */
216 str r8, [r0, #4] /* Store r0 from boot loader */
217 str r9, [r0, #8] /* Store r1 from boot loader */
218 str r10, [r0, #12] /* store r2 from boot loader */
219 str r11, [r0, #16] /* store r3 from boot loader */
220 str r5, [r0, #20] /* store the physical address */
221 adr r4, Lpagetable /* load the pagetable address */
223 str r5, [r0, #24] /* store the pagetable address */
224 mov fp, #0 /* trace back starts here */
225 bl _C_LABEL(initarm) /* Off we go */
227 /* init arm will return the new stack pointer. */
230 bl _C_LABEL(mi_startup) /* call mi_startup()! */
232 ldr r0, =.Lmainreturned
237 #define VA_TO_PA_POINTER(name, table) \
243 * Returns the physical address of a magic va to pa pointer.
244 * r0 - The pagetable data pointer. This must be built using the
245 * VA_TO_PA_POINTER macro.
247 * VA_TO_PA_POINTER(Lpagetable, pagetable)
250 * bl translate_va_to_pa
251 * r0 will now contain the physical address of pagetable
257 /* At this point: r2 = VA - PA */
260 * Find the physical address of the table. After these two
264 * r0 = va(pagetable) - (VA - PA)
265 * = va(pagetable) - VA + PA
274 * r0 - the table base address
279 /* Setup TLB and MMU registers */
280 mcr CP15_TTBR0(r0) /* Set TTB */
282 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */
284 /* Set the Domain Access register */
285 mov r0, #DOMAIN_CLIENT /* Only domain #0 is used */
289 * Set TEX remap registers
290 * - All is set to uncacheable memory
296 mcr CP15_TLBIALL /* Flush TLB */
302 orr r0, r0, #CPU_CONTROL_MMU_ENABLE
303 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
304 orr r0, r0, #CPU_CONTROL_TR_ENABLE
305 orr r0, r0, #CPU_CONTROL_AF_ENABLE
309 mcr CP15_TLBIALL /* Flush TLB */
310 mcr CP15_BPIALL /* Flush Branch predictor */
319 * Init SMP coherent mode, enable caching and switch to final MMU table.
320 * Called with disabled caches
321 * r0 - The table base address
322 * r1 - clear bits for aux register
323 * r2 - set bits for aux register
325 ASENTRY_NP(reinit_mmu)
331 /* !! Be very paranoid here !! */
332 /* !! We cannot write single bit here !! */
334 #if 0 /* XXX writeback shouldn't be necessary */
335 /* Write back and invalidate all integrated caches */
336 bl dcache_wbinv_poc_all
338 bl dcache_inv_pou_all
344 /* Set auxiliary register */
346 bic r8, r7, r5 /* Mask bits */
347 eor r8, r8, r6 /* Set bits */
355 orr r7, #CPU_CONTROL_DC_ENABLE
356 orr r7, #CPU_CONTROL_IC_ENABLE
357 orr r7, #CPU_CONTROL_BPRD_ENABLE
361 mcr CP15_TTBR0(r4) /* Set new TTB */
365 mcr CP15_TLBIALL /* Flush TLB */
366 mcr CP15_BPIALL /* Flush Branch predictor */
370 #if 0 /* XXX writeback shouldn't be necessary */
371 /* Write back and invalidate all integrated caches */
372 bl dcache_wbinv_poc_all
374 bl dcache_inv_pou_all
385 * Builds the page table
386 * r0 - The table base address
387 * r1 - The physical address (trashed)
388 * r2 - The virtual address (trashed)
389 * r3 - The number of 1MiB sections
392 * Addresses must be 1MiB aligned
394 build_device_pagetables:
395 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
398 /* Set the required page attributed */
399 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
403 /* Move the virtual address to the correct bit location */
404 lsr r2, #(PTE1_SHIFT - 2)
410 add r1, r1, #(PTE1_SIZE)
416 VA_TO_PA_POINTER(Lpagetable, boot_pt1)
418 .global _C_LABEL(hypmode_enabled)
419 _C_LABEL(hypmode_enabled):
423 .word _edata /* Note that these three items are */
424 .word _ebss /* loaded with a single ldmia and */
425 .word svcstk /* must remain in order together. */
428 .asciz "main() returned"
433 .space INIT_ARM_STACK_SIZE * MAXCPU
436 * Memory for the initial pagetable. We are unable to place this in
437 * the bss as this will be cleared after the table is loaded.
439 .section ".init_pagetable", "aw", %nobits
440 .align 14 /* 16KiB aligned */
451 /* Make sure interrupts are disabled. */
456 /* Setup core, disable all caches. */
458 bic r0, #CPU_CONTROL_MMU_ENABLE
459 bic r0, #CPU_CONTROL_AFLT_ENABLE
460 bic r0, #CPU_CONTROL_DC_ENABLE
461 bic r0, #CPU_CONTROL_IC_ENABLE
462 bic r0, #CPU_CONTROL_BPRD_ENABLE
463 bic r0, #CPU_CONTROL_SW_ENABLE
464 orr r0, #CPU_CONTROL_UNAL_ENABLE
465 orr r0, #CPU_CONTROL_VECRELOC
470 /* Invalidate L1 cache I+D cache */
471 bl dcache_inv_pou_all
476 /* Find the delta between VA and PA */
478 bl translate_va_to_pa
482 adr r1, .Lstart+8 /* Get initstack pointer from */
483 ldr sp, [r1] /* startup data. */
484 mrc CP15_MPIDR(r0) /* Get processor id number. */
486 mov r1, #INIT_ARM_STACK_SIZE
487 mul r2, r1, r0 /* Point sp to initstack */
488 add sp, sp, r2 /* area for this processor. */
490 /* Switch to virtual addresses. */
493 mov fp, #0 /* trace back starts here */
494 bl _C_LABEL(init_secondary)/* Off we go, cpu id in r0. */
502 .asciz "init_secondary() returned"
508 /* XXX re-implement !!! */
510 bl dcache_wbinv_poc_all
512 ldr r4, .Lcpu_reset_address
521 * _cpu_reset_address contains the address to branch to, to complete
522 * the cpu reset after turning the MMU off
523 * This variable is provided by the hardware specific code
526 .word _C_LABEL(cpu_reset_address)
546 .global _C_LABEL(esym)
547 _C_LABEL(esym): .word _C_LABEL(end)
558 * Call the sigreturn system call.
560 * We have to load r7 manually rather than using
561 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
562 * correct. Using the alternative places esigcode at the address
563 * of the data rather than the address one past the data.
566 ldr r7, [pc, #12] /* Load SYS_sigreturn */
569 /* Well if that failed we better exit quick ! */
571 ldr r7, [pc, #8] /* Load SYS_exit */
574 /* Branch back to retry SYS_sigreturn */
581 .global _C_LABEL(esigcode)
587 .long esigcode-sigcode
589 /* End of locore.S */