1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright 2011 Semihalf
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/syscall.h>
38 #include <machine/asm.h>
39 #include <machine/armreg.h>
40 #include <machine/cpuconf.h>
41 #include <machine/pte.h>
43 __FBSDID("$FreeBSD$");
45 /* What size should this really be ? It is only used by initarm() */
46 #define INIT_ARM_STACK_SIZE (2048 * 4)
48 #define CPWAIT_BRANCH \
52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
53 mov tmp, tmp /* wait for it to complete */ ;\
54 CPWAIT_BRANCH /* branch to next insn */
57 * This is for kvm_mkdb, and should be the address of the beginning
58 * of the kernel text segment (not necessarily the same as kernbase).
63 .set kernbase,KERNBASE
65 .set physaddr,PHYSADDR
68 * On entry for FreeBSD boot ABI:
69 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
70 * r1 - if (r0 == 0) then metadata pointer
71 * On entry for Linux boot ABI:
73 * r1 - machine type (passed as arg2 to initarm)
74 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
76 * For both types of boot we gather up the args, put them in a struct arm_boot_params
77 * structure and pass that to initarm.
82 STOP_UNWINDING /* Can't unwind into the bootloader! */
84 mov r9, r0 /* 0 or boot mode from boot2 */
85 mov r8, r1 /* Save Machine type */
86 mov ip, r2 /* Save meta data */
87 mov fp, r3 /* Future expansion */
89 /* Make sure interrupts are disabled. */
91 orr r7, r7, #(PSR_I | PSR_F)
94 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
95 /* Check if we're running from flash. */
98 * If we're running with MMU disabled, test against the
99 * physical address instead.
101 mrc p15, 0, r2, c1, c0, 0
102 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
104 ldrne r6, =LOADERRAMADDR
126 Lram_offset: .word from_ram-_C_LABEL(_start)
132 /* Disable MMU for a while */
133 mrc p15, 0, r2, c1, c0, 0
134 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
135 CPU_CONTROL_WBUF_ENABLE)
136 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
137 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
138 mcr p15, 0, r2, c1, c0, 0
147 * Build page table from scratch.
150 /* Find the delta between VA and PA */
152 bl translate_va_to_pa
156 * Some of the older ports (the various XScale, mostly) assume
157 * that the memory before the kernel is mapped, and use it for
158 * the various stacks, page tables, etc. For those CPUs, map the
159 * 64 first MB of RAM, as it used to be.
167 /* Map 64MiB, preserved over calls to build_pagetables */
171 /* Create the kernel map to jump to */
175 ldr r5, =(KERNPHYSADDR)
180 /* Find the start kernels load address */
182 ldr r2, =(L1_S_OFFSET)
186 /* Map 64MiB, preserved over calls to build_pagetables */
190 /* Create the kernel map to jump to */
192 ldr r2, =(KERNVIRTADDR)
196 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
197 /* Create the custom map */
204 orr r0, r0, #2 /* Set TTB shared memory flag */
206 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
207 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
209 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
211 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
214 /* Set the Domain Access register. Very important! */
215 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
216 mcr p15, 0, r0, c3, c0, 0
219 * On armv6 enable extended page tables, and set alignment checking
220 * to modulo-4 (CPU_CONTROL_UNAL_ENABLE) for the ldrd/strd
221 * instructions emitted by clang.
223 mrc p15, 0, r0, c1, c0, 0
225 orr r0, r0, #(CPU_CONTROL_V6_EXTPAGE | CPU_CONTROL_UNAL_ENABLE)
226 orr r0, r0, #(CPU_CONTROL_AFLT_ENABLE)
227 orr r0, r0, #(CPU_CONTROL_AF_ENABLE)
229 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
230 mcr p15, 0, r0, c1, c0, 0
239 ldmia r1, {r1, r2, sp} /* Set initial stack and */
240 sub r2, r2, r1 /* get zero init data */
243 str r3, [r1], #0x0004 /* get zero init data */
249 mov r1, #28 /* loader info size is 28 bytes also second arg */
250 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
251 mov r0, sp /* loader info pointer is first arg */
252 bic sp, sp, #7 /* align stack to 8 bytes */
253 str r1, [r0] /* Store length of loader info */
254 str r9, [r0, #4] /* Store r0 from boot loader */
255 str r8, [r0, #8] /* Store r1 from boot loader */
256 str ip, [r0, #12] /* store r2 from boot loader */
257 str fp, [r0, #16] /* store r3 from boot loader */
258 str r5, [r0, #20] /* store the physical address */
259 adr r4, Lpagetable /* load the pagetable address */
261 str r5, [r0, #24] /* store the pagetable address */
262 mov fp, #0 /* trace back starts here */
263 bl _C_LABEL(initarm) /* Off we go */
265 /* init arm will return the new stack pointer. */
268 bl _C_LABEL(mi_startup) /* call mi_startup()! */
270 adr r0, .Lmainreturned
275 #define VA_TO_PA_POINTER(name, table) \
281 * Returns the physical address of a magic va to pa pointer.
282 * r0 - The pagetable data pointer. This must be built using the
283 * VA_TO_PA_POINTER macro.
285 * VA_TO_PA_POINTER(Lpagetable, pagetable)
288 * bl translate_va_to_pa
289 * r0 will now contain the physical address of pagetable
295 /* At this point: r2 = VA - PA */
298 * Find the physical address of the table. After these two
302 * r0 = va(pagetable) - (VA - PA)
303 * = va(pagetable) - VA + PA
311 * Builds the page table
312 * r0 - The table base address
313 * r1 - The physical address (trashed)
314 * r2 - The virtual address (trashed)
315 * r3 - The number of 1MiB sections
318 * Addresses must be 1MiB aligned
321 /* Set the required page attributed */
322 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
328 /* Move the virtual address to the correct bit location */
329 lsr r2, #(L1_S_SHIFT - 2)
335 add r1, r1, #(L1_S_SIZE)
341 VA_TO_PA_POINTER(Lpagetable, pagetable)
351 .word svcstk + INIT_ARM_STACK_SIZE
357 .asciz "main() returned"
362 .space INIT_ARM_STACK_SIZE
365 * Memory for the initial pagetable. We are unable to place this in
366 * the bss as this will be cleared after the table is loaded.
368 .section ".init_pagetable"
369 .align 14 /* 16KiB aligned */
377 .word _C_LABEL(cpufuncs)
383 VA_TO_PA_POINTER(Lstartup_pagetable_secondary, temp_pagetable)
387 /* Make sure interrupts are disabled. */
389 orr r7, r7, #(PSR_I | PSR_F)
392 /* Disable MMU. It should be disabled already, but make sure. */
393 mrc p15, 0, r2, c1, c0, 0
394 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
395 CPU_CONTROL_WBUF_ENABLE)
396 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
397 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
398 mcr p15, 0, r2, c1, c0, 0
405 bl armv6_idcache_inv_all /* Modifies r0 only */
407 bl armv7_idcache_inv_all /* Modifies r0-r3, ip */
410 /* Load the page table physical address */
411 adr r0, Lstartup_pagetable_secondary
412 bl translate_va_to_pa
413 /* Load the address the secondary page table */
416 orr r0, r0, #2 /* Set TTB shared memory flag */
417 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
418 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
421 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
423 /* Set the Domain Access register. Very important! */
424 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
425 mcr p15, 0, r0, c3, c0, 0
427 mrc p15, 0, r0, c1, c0, 0
428 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
429 orr r0, r0, #CPU_CONTROL_AF_ENABLE
430 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
431 CPU_CONTROL_WBUF_ENABLE)
432 orr r0, r0, #(CPU_CONTROL_IC_ENABLE)
433 orr r0, r0, #(CPU_CONTROL_BPRD_ENABLE)
434 mcr p15, 0, r0, c1, c0, 0
441 ldmia r1, {r1, r2, sp} /* Set initial stack and */
442 mrc p15, 0, r0, c0, c0, 5
448 ldr pc, .Lmpvirt_done
452 mov fp, #0 /* trace back starts here */
453 bl _C_LABEL(init_secondary) /* Off we go */
460 .asciz "init_secondary() returned"
467 bic r2, r2, #(PSR_MODE)
468 orr r2, r2, #(PSR_SVC32_MODE)
469 orr r2, r2, #(PSR_I | PSR_F)
472 ldr r4, .Lcpu_reset_address
477 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
479 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
482 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
486 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
492 * MMU & IDC off, 32 bit program & data space
493 * Hurl ourselves into the ROM
495 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
496 mcr 15, 0, r0, c1, c0, 0
497 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
501 * _cpu_reset_address contains the address to branch to, to complete
502 * the cpu reset after turning the MMU off
503 * This variable is provided by the hardware specific code
506 .word _C_LABEL(cpu_reset_address)
509 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
510 * v4 MMU disable instruction needs executing... it is an illegal instruction
511 * on f.e. ARM6/7 that locks up the computer in an endless illegal
512 * instruction / data-abort / reset loop.
514 .Lcpu_reset_needs_v4_MMU_disable:
515 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
535 .global _C_LABEL(esym)
536 _C_LABEL(esym): .word _C_LABEL(end)
547 * Call the sigreturn system call.
549 * We have to load r7 manually rather than using
550 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
551 * correct. Using the alternative places esigcode at the address
552 * of the data rather than the address one past the data.
555 ldr r7, [pc, #12] /* Load SYS_sigreturn */
558 /* Well if that failed we better exit quick ! */
560 ldr r7, [pc, #8] /* Load SYS_exit */
563 /* Branch back to retry SYS_sigreturn */
570 .global _C_LABEL(esigcode)
576 .long esigcode-sigcode
578 /* End of locore.S */