2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/mutex.h>
40 #include <sys/sched.h>
43 #include <sys/malloc.h>
46 #include <vm/vm_extern.h>
47 #include <vm/vm_kern.h>
50 #include <machine/armreg.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/debug_monitor.h>
54 #include <machine/smp.h>
55 #include <machine/pcb.h>
56 #include <machine/physmem.h>
57 #include <machine/intr.h>
58 #include <machine/vmparam.h>
60 #include <machine/vfp.h>
63 #include <arm/mv/mvwin.h>
66 extern struct pcpu __pcpu[];
67 /* used to hold the AP's until we are ready to release them */
68 struct mtx ap_boot_mtx;
69 struct pcb stoppcbs[MAXCPU];
71 /* # of Applications processors */
74 /* Set to 1 once we're ready to let the APs out of the pen. */
75 volatile int aps_ready = 0;
77 void set_stackptrs(int cpu);
79 /* Temporary variables for init_secondary() */
80 void *dpcpu[MAXCPU - 1];
82 /* Determine if we running MP machine */
87 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
89 CPU_SETOF(0, &all_cpus);
91 return (mp_ncpus > 1);
94 /* Start Application Processor via platform specific function */
100 for (ms = 0; ms < 2000; ++ms) {
101 if ((mp_naps + 1) == mp_ncpus)
102 return (0); /* success */
110 extern unsigned char _end[];
112 /* Initialize and fire up non-boot processors */
118 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
120 /* Reserve memory for application processors */
121 for(i = 0; i < (mp_ncpus - 1); i++)
122 dpcpu[i] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
124 dcache_wbinv_poc_all();
126 /* Initialize boot code and start up processors */
127 platform_mp_start_ap();
129 /* Check if ap's started properly */
132 printf("WARNING: Some AP's failed to start\n");
134 for (i = 1; i < mp_ncpus; i++)
135 CPU_SET(i, &all_cpus);
138 /* Introduce rest of cores to the world */
140 cpu_mp_announce(void)
145 extern vm_paddr_t pmap_pa;
147 init_secondary(int cpu)
150 uint32_t loop_counter;
153 cpuinfo_reinit_mmu(pmap_kern_ttb);
156 /* Provide stack pointers for other processor modes. */
159 enable_interrupts(PSR_A);
163 * pcpu_init() updates queue, so it should not be executed in parallel
166 while(mp_naps < (cpu - 1))
169 pcpu_init(pc, cpu, sizeof(struct pcpu));
170 dpcpu_init(dpcpu[cpu - 1], cpu);
171 #if __ARM_ARCH >= 6 && defined(DDB)
172 dbg_monitor_init_secondary();
174 /* Signal our startup to BSP */
175 atomic_add_rel_32(&mp_naps, 1);
177 /* Spin until the BSP releases the APs */
178 while (!atomic_load_acq_int(&aps_ready)) {
180 __asm __volatile("wfe");
184 /* Initialize curthread */
185 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
186 pc->pc_curthread = pc->pc_idlethread;
187 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
188 set_curthread(pc->pc_idlethread);
193 /* Configure the interrupt controller */
194 intr_pic_init_secondary();
196 /* Apply possible BP hardening */
197 cpuinfo_init_bp_hardening();
199 mtx_lock_spin(&ap_boot_mtx);
201 atomic_add_rel_32(&smp_cpus, 1);
203 if (smp_cpus == mp_ncpus) {
204 /* enable IPI's, tlb shootdown, freezes etc */
205 atomic_store_rel_int(&smp_started, 1);
208 mtx_unlock_spin(&ap_boot_mtx);
210 enable_interrupts(PSR_I);
213 while (smp_started == 0) {
216 if (loop_counter == 1000)
217 CTR0(KTR_SMP, "AP still wait for smp_started");
219 /* Start per-CPU event timers. */
222 CTR0(KTR_SMP, "go into scheduler");
224 /* Enter the scheduler */
227 panic("scheduler returned us to %s", __func__);
232 ipi_rendezvous(void *dummy __unused)
235 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
236 smp_rendezvous_action();
240 ipi_ast(void *dummy __unused)
243 CTR0(KTR_SMP, "IPI_AST");
247 ipi_stop(void *dummy __unused)
252 * IPI_STOP_HARD is mapped to IPI_STOP.
254 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
256 cpu = PCPU_GET(cpuid);
257 savectx(&stoppcbs[cpu]);
260 * CPUs are stopped when entering the debugger and at
261 * system shutdown, both events which can precede a
262 * panic dump. For the dump to be correct, all caches
263 * must be flushed and invalidated, but on ARM there's
264 * no way to broadcast a wbinv_all to other cores.
265 * Instead, we have each core do the local wbinv_all as
266 * part of stopping the core. The core requesting the
267 * stop will do the l2 cache flush after all other cores
268 * have done their l1 flushes and stopped.
270 dcache_wbinv_poc_all();
272 /* Indicate we are stopped */
273 CPU_SET_ATOMIC(cpu, &stopped_cpus);
275 /* Wait for restart */
276 while (!CPU_ISSET(cpu, &started_cpus))
279 CPU_CLR_ATOMIC(cpu, &started_cpus);
280 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
284 CTR0(KTR_SMP, "IPI_STOP (restart)");
288 ipi_preempt(void *arg)
290 struct trapframe *oldframe;
295 td->td_intr_nesting_level++;
296 oldframe = td->td_intr_frame;
297 td->td_intr_frame = (struct trapframe *)arg;
299 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
302 td->td_intr_frame = oldframe;
303 td->td_intr_nesting_level--;
308 ipi_hardclock(void *arg)
310 struct trapframe *oldframe;
315 td->td_intr_nesting_level++;
316 oldframe = td->td_intr_frame;
317 td->td_intr_frame = (struct trapframe *)arg;
319 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
322 td->td_intr_frame = oldframe;
323 td->td_intr_nesting_level--;
328 release_aps(void *dummy __unused)
330 uint32_t loop_counter;
335 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
336 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
337 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
338 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
339 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
341 atomic_store_rel_int(&aps_ready, 1);
342 /* Wake the other threads up */
346 printf("Release APs\n");
348 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
353 printf("AP's not started\n");
356 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
362 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
366 cpu_mp_setmaxid(void)
369 platform_mp_setmaxid();
374 ipi_all_but_self(u_int ipi)
378 other_cpus = all_cpus;
379 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
380 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
381 intr_ipi_send(other_cpus, ipi);
385 ipi_cpu(int cpu, u_int ipi)
392 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
393 intr_ipi_send(cpus, ipi);
397 ipi_selected(cpuset_t cpus, u_int ipi)
400 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
401 intr_ipi_send(cpus, ipi);