2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
31 #include <sys/kernel.h>
33 #include <sys/mutex.h>
36 #include <sys/sched.h>
39 #include <sys/malloc.h>
42 #include <vm/vm_extern.h>
43 #include <vm/vm_kern.h>
46 #include <machine/armreg.h>
47 #include <machine/cpu.h>
48 #include <machine/cpufunc.h>
49 #include <machine/smp.h>
50 #include <machine/pcb.h>
51 #include <machine/pmap.h>
52 #include <machine/pte.h>
53 #include <machine/physmem.h>
54 #include <machine/intr.h>
55 #include <machine/vmparam.h>
57 #include <machine/vfp.h>
60 #include <arm/mv/mvwin.h>
61 #include <dev/fdt/fdt_common.h>
66 extern struct pcpu __pcpu[];
67 /* used to hold the AP's until we are ready to release them */
68 struct mtx ap_boot_mtx;
69 struct pcb stoppcbs[MAXCPU];
71 /* # of Applications processors */
74 /* Set to 1 once we're ready to let the APs out of the pen. */
75 volatile int aps_ready = 0;
78 static int ipi_handler(void *arg);
80 void set_stackptrs(int cpu);
82 /* Temporary variables for init_secondary() */
83 void *dpcpu[MAXCPU - 1];
85 /* Determine if we running MP machine */
89 CPU_SETOF(0, &all_cpus);
91 return (platform_mp_probe());
94 /* Start Application Processor via platform specific function */
100 for (ms = 0; ms < 2000; ++ms) {
101 if ((mp_naps + 1) == mp_ncpus)
102 return (0); /* success */
110 extern unsigned char _end[];
112 /* Initialize and fire up non-boot processors */
118 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
120 /* Reserve memory for application processors */
121 for(i = 0; i < (mp_ncpus - 1); i++)
122 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
125 cpu_idcache_wbinv_all();
126 cpu_l2cache_wbinv_all();
127 cpu_idcache_wbinv_all();
129 /* Initialize boot code and start up processors */
130 platform_mp_start_ap();
132 /* Check if ap's started properly */
135 printf("WARNING: Some AP's failed to start\n");
137 for (i = 1; i < mp_ncpus; i++)
138 CPU_SET(i, &all_cpus);
141 /* Introduce rest of cores to the world */
143 cpu_mp_announce(void)
148 extern vm_paddr_t pmap_pa;
150 init_secondary(int cpu)
153 uint32_t loop_counter;
155 int start = 0, end = 0;
158 uint32_t actlr_mask, actlr_set;
161 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
162 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
165 /* Provide stack pointers for other processor modes. */
168 enable_interrupts(PSR_A);
169 #else /* ARM_NEW_PMAP */
173 #endif /* ARM_NEW_PMAP */
177 * pcpu_init() updates queue, so it should not be executed in parallel
180 while(mp_naps < (cpu - 1))
183 pcpu_init(pc, cpu, sizeof(struct pcpu));
184 dpcpu_init(dpcpu[cpu - 1], cpu);
186 /* Provide stack pointers for other processor modes. */
189 /* Signal our startup to BSP */
190 atomic_add_rel_32(&mp_naps, 1);
192 /* Spin until the BSP releases the APs */
193 while (!atomic_load_acq_int(&aps_ready)) {
195 __asm __volatile("wfe");
199 /* Initialize curthread */
200 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
201 pc->pc_curthread = pc->pc_idlethread;
202 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
203 set_curthread(pc->pc_idlethread);
208 mtx_lock_spin(&ap_boot_mtx);
210 atomic_add_rel_32(&smp_cpus, 1);
212 if (smp_cpus == mp_ncpus) {
213 /* enable IPI's, tlb shootdown, freezes etc */
214 atomic_store_rel_int(&smp_started, 1);
217 mtx_unlock_spin(&ap_boot_mtx);
222 start = IPI_IRQ_START;
230 for (int i = start; i <= end; i++)
233 enable_interrupts(PSR_I);
236 while (smp_started == 0) {
239 if (loop_counter == 1000)
240 CTR0(KTR_SMP, "AP still wait for smp_started");
242 /* Start per-CPU event timers. */
245 CTR0(KTR_SMP, "go into scheduler");
246 platform_mp_init_secondary();
248 /* Enter the scheduler */
251 panic("scheduler returned us to %s", __func__);
257 ipi_rendezvous(void *dummy __unused)
260 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
261 smp_rendezvous_action();
265 ipi_ast(void *dummy __unused)
268 CTR0(KTR_SMP, "IPI_AST");
272 ipi_stop(void *dummy __unused)
277 * IPI_STOP_HARD is mapped to IPI_STOP.
279 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
281 cpu = PCPU_GET(cpuid);
282 savectx(&stoppcbs[cpu]);
285 * CPUs are stopped when entering the debugger and at
286 * system shutdown, both events which can precede a
287 * panic dump. For the dump to be correct, all caches
288 * must be flushed and invalidated, but on ARM there's
289 * no way to broadcast a wbinv_all to other cores.
290 * Instead, we have each core do the local wbinv_all as
291 * part of stopping the core. The core requesting the
292 * stop will do the l2 cache flush after all other cores
293 * have done their l1 flushes and stopped.
295 cpu_idcache_wbinv_all();
297 /* Indicate we are stopped */
298 CPU_SET_ATOMIC(cpu, &stopped_cpus);
300 /* Wait for restart */
301 while (!CPU_ISSET(cpu, &started_cpus))
304 CPU_CLR_ATOMIC(cpu, &started_cpus);
305 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
306 CTR0(KTR_SMP, "IPI_STOP (restart)");
310 ipi_preempt(void *arg)
312 struct trapframe *oldframe;
317 td->td_intr_nesting_level++;
318 oldframe = td->td_intr_frame;
319 td->td_intr_frame = (struct trapframe *)arg;
321 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
324 td->td_intr_frame = oldframe;
325 td->td_intr_nesting_level--;
330 ipi_hardclock(void *arg)
332 struct trapframe *oldframe;
337 td->td_intr_nesting_level++;
338 oldframe = td->td_intr_frame;
339 td->td_intr_frame = (struct trapframe *)arg;
341 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
344 td->td_intr_frame = oldframe;
345 td->td_intr_nesting_level--;
350 ipi_tlb(void *dummy __unused)
353 CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
354 cpufuncs.cf_tlb_flushID();
358 ipi_handler(void *arg)
362 cpu = PCPU_GET(cpuid);
364 ipi = pic_ipi_read((int)arg);
366 while ((ipi != 0x3ff)) {
369 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
370 smp_rendezvous_action();
374 CTR0(KTR_SMP, "IPI_AST");
379 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
380 * necessary to add it in the switch.
382 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
384 savectx(&stoppcbs[cpu]);
387 * CPUs are stopped when entering the debugger and at
388 * system shutdown, both events which can precede a
389 * panic dump. For the dump to be correct, all caches
390 * must be flushed and invalidated, but on ARM there's
391 * no way to broadcast a wbinv_all to other cores.
392 * Instead, we have each core do the local wbinv_all as
393 * part of stopping the core. The core requesting the
394 * stop will do the l2 cache flush after all other cores
395 * have done their l1 flushes and stopped.
397 cpu_idcache_wbinv_all();
399 /* Indicate we are stopped */
400 CPU_SET_ATOMIC(cpu, &stopped_cpus);
402 /* Wait for restart */
403 while (!CPU_ISSET(cpu, &started_cpus))
406 CPU_CLR_ATOMIC(cpu, &started_cpus);
407 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
408 CTR0(KTR_SMP, "IPI_STOP (restart)");
411 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
412 sched_preempt(curthread);
415 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
419 CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
420 cpufuncs.cf_tlb_flushID();
423 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
427 ipi = pic_ipi_read(-1);
430 return (FILTER_HANDLED);
435 release_aps(void *dummy __unused)
437 uint32_t loop_counter;
439 int start = 0, end = 0;
446 intr_ipi_set_handler(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL, 0);
447 intr_ipi_set_handler(IPI_AST, "ast", ipi_ast, NULL, 0);
448 intr_ipi_set_handler(IPI_STOP, "stop", ipi_stop, NULL, 0);
449 intr_ipi_set_handler(IPI_PREEMPT, "preempt", ipi_preempt, NULL, 0);
450 intr_ipi_set_handler(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL, 0);
451 intr_ipi_set_handler(IPI_TLB, "tlb", ipi_tlb, NULL, 0);
455 start = IPI_IRQ_START;
463 for (int i = start; i <= end; i++) {
468 * Use 0xdeadbeef as the argument value for irq 0,
469 * if we used 0, the intr code will give the trap frame
472 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
473 INTR_TYPE_MISC | INTR_EXCL, NULL);
479 atomic_store_rel_int(&aps_ready, 1);
480 /* Wake the other threads up */
485 printf("Release APs\n");
487 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
492 printf("AP's not started\n");
495 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
501 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
505 cpu_mp_setmaxid(void)
508 platform_mp_setmaxid();
513 ipi_all_but_self(u_int ipi)
517 other_cpus = all_cpus;
518 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
519 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
520 platform_ipi_send(other_cpus, ipi);
524 ipi_cpu(int cpu, u_int ipi)
531 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
532 platform_ipi_send(cpus, ipi);
536 ipi_selected(cpuset_t cpus, u_int ipi)
539 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
540 platform_ipi_send(cpus, ipi);
544 tlb_broadcast(int ipi)
548 ipi_all_but_self(ipi);