2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/mutex.h>
40 #include <sys/sched.h>
43 #include <sys/malloc.h>
46 #include <vm/vm_extern.h>
47 #include <vm/vm_kern.h>
50 #include <machine/armreg.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/debug_monitor.h>
54 #include <machine/smp.h>
55 #include <machine/pcb.h>
56 #include <machine/physmem.h>
57 #include <machine/intr.h>
58 #include <machine/vmparam.h>
60 #include <machine/vfp.h>
63 #include <arm/mv/mvwin.h>
66 /* used to hold the AP's until we are ready to release them */
67 struct mtx ap_boot_mtx;
68 struct pcb stoppcbs[MAXCPU];
70 /* # of Applications processors */
73 /* Set to 1 once we're ready to let the APs out of the pen. */
74 volatile int aps_ready = 0;
76 void set_stackptrs(int cpu);
78 /* Temporary variables for init_secondary() */
79 void *dpcpu[MAXCPU - 1];
81 /* Determine if we running MP machine */
86 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
88 CPU_SETOF(0, &all_cpus);
90 return (mp_ncpus > 1);
93 /* Start Application Processor via platform specific function */
99 for (ms = 0; ms < 2000; ++ms) {
100 if ((mp_naps + 1) == mp_ncpus)
101 return (0); /* success */
109 /* Initialize and fire up non-boot processors */
115 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
117 /* Reserve memory for application processors */
118 for(i = 0; i < (mp_ncpus - 1); i++)
119 dpcpu[i] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
121 dcache_wbinv_poc_all();
123 /* Initialize boot code and start up processors */
124 platform_mp_start_ap();
126 /* Check if ap's started properly */
129 printf("WARNING: Some AP's failed to start\n");
131 for (i = 1; i < mp_ncpus; i++)
132 CPU_SET(i, &all_cpus);
135 /* Introduce rest of cores to the world */
137 cpu_mp_announce(void)
142 extern vm_paddr_t pmap_pa;
144 init_secondary(int cpu)
147 uint32_t loop_counter;
150 cpuinfo_reinit_mmu(pmap_kern_ttb);
153 /* Provide stack pointers for other processor modes. */
156 enable_interrupts(PSR_A);
160 * pcpu_init() updates queue, so it should not be executed in parallel
163 while(mp_naps < (cpu - 1))
166 pcpu_init(pc, cpu, sizeof(struct pcpu));
167 dpcpu_init(dpcpu[cpu - 1], cpu);
168 #if __ARM_ARCH >= 6 && defined(DDB)
169 dbg_monitor_init_secondary();
171 /* Signal our startup to BSP */
172 atomic_add_rel_32(&mp_naps, 1);
174 /* Spin until the BSP releases the APs */
175 while (!atomic_load_acq_int(&aps_ready)) {
177 __asm __volatile("wfe");
181 /* Initialize curthread */
182 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
183 pc->pc_curthread = pc->pc_idlethread;
184 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
185 set_curthread(pc->pc_idlethread);
190 /* Configure the interrupt controller */
191 intr_pic_init_secondary();
193 /* Apply possible BP hardening */
194 cpuinfo_init_bp_hardening();
196 mtx_lock_spin(&ap_boot_mtx);
198 atomic_add_rel_32(&smp_cpus, 1);
200 if (smp_cpus == mp_ncpus) {
201 /* enable IPI's, tlb shootdown, freezes etc */
202 atomic_store_rel_int(&smp_started, 1);
205 mtx_unlock_spin(&ap_boot_mtx);
207 enable_interrupts(PSR_I);
210 while (smp_started == 0) {
213 if (loop_counter == 1000)
214 CTR0(KTR_SMP, "AP still wait for smp_started");
216 /* Start per-CPU event timers. */
219 CTR0(KTR_SMP, "go into scheduler");
221 /* Enter the scheduler */
224 panic("scheduler returned us to %s", __func__);
229 ipi_rendezvous(void *dummy __unused)
232 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
233 smp_rendezvous_action();
237 ipi_ast(void *dummy __unused)
240 CTR0(KTR_SMP, "IPI_AST");
244 ipi_stop(void *dummy __unused)
249 * IPI_STOP_HARD is mapped to IPI_STOP.
251 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
253 cpu = PCPU_GET(cpuid);
254 savectx(&stoppcbs[cpu]);
257 * CPUs are stopped when entering the debugger and at
258 * system shutdown, both events which can precede a
259 * panic dump. For the dump to be correct, all caches
260 * must be flushed and invalidated, but on ARM there's
261 * no way to broadcast a wbinv_all to other cores.
262 * Instead, we have each core do the local wbinv_all as
263 * part of stopping the core. The core requesting the
264 * stop will do the l2 cache flush after all other cores
265 * have done their l1 flushes and stopped.
267 dcache_wbinv_poc_all();
269 /* Indicate we are stopped */
270 CPU_SET_ATOMIC(cpu, &stopped_cpus);
272 /* Wait for restart */
273 while (!CPU_ISSET(cpu, &started_cpus))
276 CPU_CLR_ATOMIC(cpu, &started_cpus);
277 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
281 CTR0(KTR_SMP, "IPI_STOP (restart)");
285 ipi_preempt(void *arg)
287 struct trapframe *oldframe;
292 td->td_intr_nesting_level++;
293 oldframe = td->td_intr_frame;
294 td->td_intr_frame = (struct trapframe *)arg;
296 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
299 td->td_intr_frame = oldframe;
300 td->td_intr_nesting_level--;
305 ipi_hardclock(void *arg)
307 struct trapframe *oldframe;
312 td->td_intr_nesting_level++;
313 oldframe = td->td_intr_frame;
314 td->td_intr_frame = (struct trapframe *)arg;
316 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
319 td->td_intr_frame = oldframe;
320 td->td_intr_nesting_level--;
325 release_aps(void *dummy __unused)
327 uint32_t loop_counter;
332 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
333 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
334 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
335 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
336 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
338 atomic_store_rel_int(&aps_ready, 1);
339 /* Wake the other threads up */
343 printf("Release APs\n");
345 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
350 printf("AP's not started\n");
353 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
359 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
363 cpu_mp_setmaxid(void)
366 platform_mp_setmaxid();
371 ipi_all_but_self(u_int ipi)
375 other_cpus = all_cpus;
376 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
377 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
378 intr_ipi_send(other_cpus, ipi);
382 ipi_cpu(int cpu, u_int ipi)
389 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
390 intr_ipi_send(cpus, ipi);
394 ipi_selected(cpuset_t cpus, u_int ipi)
397 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
398 intr_ipi_send(cpus, ipi);