2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/mutex.h>
41 #include <sys/sched.h>
44 #include <sys/malloc.h>
47 #include <vm/vm_extern.h>
48 #include <vm/vm_kern.h>
51 #include <machine/armreg.h>
52 #include <machine/cpu.h>
53 #include <machine/cpufunc.h>
54 #include <machine/debug_monitor.h>
55 #include <machine/smp.h>
56 #include <machine/pcb.h>
57 #include <machine/physmem.h>
58 #include <machine/intr.h>
59 #include <machine/vmparam.h>
61 #include <machine/vfp.h>
64 #include <arm/mv/mvwin.h>
67 extern struct pcpu __pcpu[];
68 /* used to hold the AP's until we are ready to release them */
69 struct mtx ap_boot_mtx;
70 struct pcb stoppcbs[MAXCPU];
72 /* # of Applications processors */
75 /* Set to 1 once we're ready to let the APs out of the pen. */
76 volatile int aps_ready = 0;
79 static int ipi_handler(void *arg);
81 void set_stackptrs(int cpu);
83 /* Temporary variables for init_secondary() */
84 void *dpcpu[MAXCPU - 1];
86 /* Determine if we running MP machine */
91 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
93 CPU_SETOF(0, &all_cpus);
95 return (mp_ncpus > 1);
98 /* Start Application Processor via platform specific function */
104 for (ms = 0; ms < 2000; ++ms) {
105 if ((mp_naps + 1) == mp_ncpus)
106 return (0); /* success */
114 extern unsigned char _end[];
116 /* Initialize and fire up non-boot processors */
122 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
124 /* Reserve memory for application processors */
125 for(i = 0; i < (mp_ncpus - 1); i++)
126 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
129 dcache_wbinv_poc_all();
131 /* Initialize boot code and start up processors */
132 platform_mp_start_ap();
134 /* Check if ap's started properly */
137 printf("WARNING: Some AP's failed to start\n");
139 for (i = 1; i < mp_ncpus; i++)
140 CPU_SET(i, &all_cpus);
143 /* Introduce rest of cores to the world */
145 cpu_mp_announce(void)
150 extern vm_paddr_t pmap_pa;
152 init_secondary(int cpu)
155 uint32_t loop_counter;
157 int start = 0, end = 0;
161 cpuinfo_reinit_mmu(pmap_kern_ttb);
164 /* Provide stack pointers for other processor modes. */
167 enable_interrupts(PSR_A);
171 * pcpu_init() updates queue, so it should not be executed in parallel
174 while(mp_naps < (cpu - 1))
177 pcpu_init(pc, cpu, sizeof(struct pcpu));
178 dpcpu_init(dpcpu[cpu - 1], cpu);
179 #if __ARM_ARCH >= 6 && defined(DDB)
180 dbg_monitor_init_secondary();
182 /* Signal our startup to BSP */
183 atomic_add_rel_32(&mp_naps, 1);
185 /* Spin until the BSP releases the APs */
186 while (!atomic_load_acq_int(&aps_ready)) {
188 __asm __volatile("wfe");
192 /* Initialize curthread */
193 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
194 pc->pc_curthread = pc->pc_idlethread;
195 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
196 set_curthread(pc->pc_idlethread);
201 /* Configure the interrupt controller */
202 intr_pic_init_secondary();
204 /* Apply possible BP hardening */
205 cpuinfo_init_bp_hardening();
207 mtx_lock_spin(&ap_boot_mtx);
209 atomic_add_rel_32(&smp_cpus, 1);
211 if (smp_cpus == mp_ncpus) {
212 /* enable IPI's, tlb shootdown, freezes etc */
213 atomic_store_rel_int(&smp_started, 1);
216 mtx_unlock_spin(&ap_boot_mtx);
221 start = IPI_IRQ_START;
229 for (int i = start; i <= end; i++)
232 enable_interrupts(PSR_I);
235 while (smp_started == 0) {
238 if (loop_counter == 1000)
239 CTR0(KTR_SMP, "AP still wait for smp_started");
241 /* Start per-CPU event timers. */
244 CTR0(KTR_SMP, "go into scheduler");
246 /* Enter the scheduler */
249 panic("scheduler returned us to %s", __func__);
255 ipi_rendezvous(void *dummy __unused)
258 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
259 smp_rendezvous_action();
263 ipi_ast(void *dummy __unused)
266 CTR0(KTR_SMP, "IPI_AST");
270 ipi_stop(void *dummy __unused)
275 * IPI_STOP_HARD is mapped to IPI_STOP.
277 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
279 cpu = PCPU_GET(cpuid);
280 savectx(&stoppcbs[cpu]);
283 * CPUs are stopped when entering the debugger and at
284 * system shutdown, both events which can precede a
285 * panic dump. For the dump to be correct, all caches
286 * must be flushed and invalidated, but on ARM there's
287 * no way to broadcast a wbinv_all to other cores.
288 * Instead, we have each core do the local wbinv_all as
289 * part of stopping the core. The core requesting the
290 * stop will do the l2 cache flush after all other cores
291 * have done their l1 flushes and stopped.
293 dcache_wbinv_poc_all();
295 /* Indicate we are stopped */
296 CPU_SET_ATOMIC(cpu, &stopped_cpus);
298 /* Wait for restart */
299 while (!CPU_ISSET(cpu, &started_cpus))
302 CPU_CLR_ATOMIC(cpu, &started_cpus);
303 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
307 CTR0(KTR_SMP, "IPI_STOP (restart)");
311 ipi_preempt(void *arg)
313 struct trapframe *oldframe;
318 td->td_intr_nesting_level++;
319 oldframe = td->td_intr_frame;
320 td->td_intr_frame = (struct trapframe *)arg;
322 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
325 td->td_intr_frame = oldframe;
326 td->td_intr_nesting_level--;
331 ipi_hardclock(void *arg)
333 struct trapframe *oldframe;
338 td->td_intr_nesting_level++;
339 oldframe = td->td_intr_frame;
340 td->td_intr_frame = (struct trapframe *)arg;
342 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
345 td->td_intr_frame = oldframe;
346 td->td_intr_nesting_level--;
352 ipi_handler(void *arg)
356 cpu = PCPU_GET(cpuid);
358 ipi = pic_ipi_read((int)arg);
360 while ((ipi != 0x3ff)) {
363 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
364 smp_rendezvous_action();
368 CTR0(KTR_SMP, "IPI_AST");
373 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
374 * necessary to add it in the switch.
376 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
378 savectx(&stoppcbs[cpu]);
381 * CPUs are stopped when entering the debugger and at
382 * system shutdown, both events which can precede a
383 * panic dump. For the dump to be correct, all caches
384 * must be flushed and invalidated, but on ARM there's
385 * no way to broadcast a wbinv_all to other cores.
386 * Instead, we have each core do the local wbinv_all as
387 * part of stopping the core. The core requesting the
388 * stop will do the l2 cache flush after all other cores
389 * have done their l1 flushes and stopped.
391 dcache_wbinv_poc_all();
393 /* Indicate we are stopped */
394 CPU_SET_ATOMIC(cpu, &stopped_cpus);
396 /* Wait for restart */
397 while (!CPU_ISSET(cpu, &started_cpus))
400 CPU_CLR_ATOMIC(cpu, &started_cpus);
401 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
405 CTR0(KTR_SMP, "IPI_STOP (restart)");
408 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
409 sched_preempt(curthread);
412 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
416 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
420 ipi = pic_ipi_read(-1);
423 return (FILTER_HANDLED);
428 release_aps(void *dummy __unused)
430 uint32_t loop_counter;
432 int start = 0, end = 0;
439 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
440 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
441 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
442 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
443 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
446 start = IPI_IRQ_START;
454 for (int i = start; i <= end; i++) {
459 * Use 0xdeadbeef as the argument value for irq 0,
460 * if we used 0, the intr code will give the trap frame
463 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
464 INTR_TYPE_MISC | INTR_EXCL, NULL);
470 atomic_store_rel_int(&aps_ready, 1);
471 /* Wake the other threads up */
475 printf("Release APs\n");
477 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
482 printf("AP's not started\n");
485 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
491 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
495 cpu_mp_setmaxid(void)
498 platform_mp_setmaxid();
503 ipi_all_but_self(u_int ipi)
507 other_cpus = all_cpus;
508 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
509 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
511 intr_ipi_send(other_cpus, ipi);
513 pic_ipi_send(other_cpus, ipi);
518 ipi_cpu(int cpu, u_int ipi)
525 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
527 intr_ipi_send(cpus, ipi);
529 pic_ipi_send(cpus, ipi);
534 ipi_selected(cpuset_t cpus, u_int ipi)
537 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
539 intr_ipi_send(cpus, ipi);
541 pic_ipi_send(cpus, ipi);