2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
31 #include <sys/kernel.h>
33 #include <sys/mutex.h>
36 #include <sys/sched.h>
39 #include <sys/malloc.h>
42 #include <vm/vm_extern.h>
43 #include <vm/vm_kern.h>
46 #include <machine/acle-compat.h>
47 #include <machine/armreg.h>
48 #include <machine/cpu.h>
49 #include <machine/cpufunc.h>
50 #include <machine/debug_monitor.h>
51 #include <machine/smp.h>
52 #include <machine/pcb.h>
53 #include <machine/physmem.h>
54 #include <machine/intr.h>
55 #include <machine/vmparam.h>
57 #include <machine/vfp.h>
60 #include <arm/mv/mvwin.h>
61 #include <dev/fdt/fdt_common.h>
66 extern struct pcpu __pcpu[];
67 /* used to hold the AP's until we are ready to release them */
68 struct mtx ap_boot_mtx;
69 struct pcb stoppcbs[MAXCPU];
71 /* # of Applications processors */
74 /* Set to 1 once we're ready to let the APs out of the pen. */
75 volatile int aps_ready = 0;
78 static int ipi_handler(void *arg);
80 void set_stackptrs(int cpu);
82 /* Temporary variables for init_secondary() */
83 void *dpcpu[MAXCPU - 1];
85 /* Determine if we running MP machine */
90 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
92 CPU_SETOF(0, &all_cpus);
94 return (mp_ncpus > 1);
97 /* Start Application Processor via platform specific function */
103 for (ms = 0; ms < 2000; ++ms) {
104 if ((mp_naps + 1) == mp_ncpus)
105 return (0); /* success */
113 extern unsigned char _end[];
115 /* Initialize and fire up non-boot processors */
121 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
123 /* Reserve memory for application processors */
124 for(i = 0; i < (mp_ncpus - 1); i++)
125 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
128 dcache_wbinv_poc_all();
130 /* Initialize boot code and start up processors */
131 platform_mp_start_ap();
133 /* Check if ap's started properly */
136 printf("WARNING: Some AP's failed to start\n");
138 for (i = 1; i < mp_ncpus; i++)
139 CPU_SET(i, &all_cpus);
142 /* Introduce rest of cores to the world */
144 cpu_mp_announce(void)
149 extern vm_paddr_t pmap_pa;
151 init_secondary(int cpu)
154 uint32_t loop_counter;
156 int start = 0, end = 0;
158 uint32_t actlr_mask, actlr_set;
161 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
162 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
165 /* Provide stack pointers for other processor modes. */
168 enable_interrupts(PSR_A);
172 * pcpu_init() updates queue, so it should not be executed in parallel
175 while(mp_naps < (cpu - 1))
178 pcpu_init(pc, cpu, sizeof(struct pcpu));
179 dpcpu_init(dpcpu[cpu - 1], cpu);
180 /* Signal our startup to BSP */
181 atomic_add_rel_32(&mp_naps, 1);
183 /* Spin until the BSP releases the APs */
184 while (!atomic_load_acq_int(&aps_ready)) {
186 __asm __volatile("wfe");
190 /* Initialize curthread */
191 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
192 pc->pc_curthread = pc->pc_idlethread;
193 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
194 set_curthread(pc->pc_idlethread);
199 mtx_lock_spin(&ap_boot_mtx);
201 atomic_add_rel_32(&smp_cpus, 1);
203 if (smp_cpus == mp_ncpus) {
204 /* enable IPI's, tlb shootdown, freezes etc */
205 atomic_store_rel_int(&smp_started, 1);
208 mtx_unlock_spin(&ap_boot_mtx);
213 start = IPI_IRQ_START;
221 for (int i = start; i <= end; i++)
224 enable_interrupts(PSR_I);
227 while (smp_started == 0) {
230 if (loop_counter == 1000)
231 CTR0(KTR_SMP, "AP still wait for smp_started");
233 /* Start per-CPU event timers. */
236 CTR0(KTR_SMP, "go into scheduler");
237 intr_pic_init_secondary();
239 /* Enter the scheduler */
242 panic("scheduler returned us to %s", __func__);
248 ipi_rendezvous(void *dummy __unused)
251 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
252 smp_rendezvous_action();
256 ipi_ast(void *dummy __unused)
259 CTR0(KTR_SMP, "IPI_AST");
263 ipi_stop(void *dummy __unused)
268 * IPI_STOP_HARD is mapped to IPI_STOP.
270 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
272 cpu = PCPU_GET(cpuid);
273 savectx(&stoppcbs[cpu]);
276 * CPUs are stopped when entering the debugger and at
277 * system shutdown, both events which can precede a
278 * panic dump. For the dump to be correct, all caches
279 * must be flushed and invalidated, but on ARM there's
280 * no way to broadcast a wbinv_all to other cores.
281 * Instead, we have each core do the local wbinv_all as
282 * part of stopping the core. The core requesting the
283 * stop will do the l2 cache flush after all other cores
284 * have done their l1 flushes and stopped.
286 dcache_wbinv_poc_all();
288 /* Indicate we are stopped */
289 CPU_SET_ATOMIC(cpu, &stopped_cpus);
291 /* Wait for restart */
292 while (!CPU_ISSET(cpu, &started_cpus))
295 CPU_CLR_ATOMIC(cpu, &started_cpus);
296 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
300 CTR0(KTR_SMP, "IPI_STOP (restart)");
304 ipi_preempt(void *arg)
306 struct trapframe *oldframe;
311 td->td_intr_nesting_level++;
312 oldframe = td->td_intr_frame;
313 td->td_intr_frame = (struct trapframe *)arg;
315 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
318 td->td_intr_frame = oldframe;
319 td->td_intr_nesting_level--;
324 ipi_hardclock(void *arg)
326 struct trapframe *oldframe;
331 td->td_intr_nesting_level++;
332 oldframe = td->td_intr_frame;
333 td->td_intr_frame = (struct trapframe *)arg;
335 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
338 td->td_intr_frame = oldframe;
339 td->td_intr_nesting_level--;
345 ipi_handler(void *arg)
349 cpu = PCPU_GET(cpuid);
351 ipi = pic_ipi_read((int)arg);
353 while ((ipi != 0x3ff)) {
356 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
357 smp_rendezvous_action();
361 CTR0(KTR_SMP, "IPI_AST");
366 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
367 * necessary to add it in the switch.
369 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
371 savectx(&stoppcbs[cpu]);
374 * CPUs are stopped when entering the debugger and at
375 * system shutdown, both events which can precede a
376 * panic dump. For the dump to be correct, all caches
377 * must be flushed and invalidated, but on ARM there's
378 * no way to broadcast a wbinv_all to other cores.
379 * Instead, we have each core do the local wbinv_all as
380 * part of stopping the core. The core requesting the
381 * stop will do the l2 cache flush after all other cores
382 * have done their l1 flushes and stopped.
384 dcache_wbinv_poc_all();
386 /* Indicate we are stopped */
387 CPU_SET_ATOMIC(cpu, &stopped_cpus);
389 /* Wait for restart */
390 while (!CPU_ISSET(cpu, &started_cpus))
393 CPU_CLR_ATOMIC(cpu, &started_cpus);
394 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
398 CTR0(KTR_SMP, "IPI_STOP (restart)");
401 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
402 sched_preempt(curthread);
405 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
409 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
413 ipi = pic_ipi_read(-1);
416 return (FILTER_HANDLED);
421 release_aps(void *dummy __unused)
423 uint32_t loop_counter;
425 int start = 0, end = 0;
432 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
433 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
434 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
435 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
436 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
439 start = IPI_IRQ_START;
447 for (int i = start; i <= end; i++) {
452 * Use 0xdeadbeef as the argument value for irq 0,
453 * if we used 0, the intr code will give the trap frame
456 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
457 INTR_TYPE_MISC | INTR_EXCL, NULL);
463 atomic_store_rel_int(&aps_ready, 1);
464 /* Wake the other threads up */
469 printf("Release APs\n");
471 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
476 printf("AP's not started\n");
479 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
485 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
489 cpu_mp_setmaxid(void)
492 platform_mp_setmaxid();
497 ipi_all_but_self(u_int ipi)
501 other_cpus = all_cpus;
502 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
503 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
505 intr_ipi_send(other_cpus, ipi);
507 pic_ipi_send(other_cpus, ipi);
512 ipi_cpu(int cpu, u_int ipi)
519 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
521 intr_ipi_send(cpus, ipi);
523 pic_ipi_send(cpus, ipi);
528 ipi_selected(cpuset_t cpus, u_int ipi)
531 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
533 intr_ipi_send(cpus, ipi);
535 pic_ipi_send(cpus, ipi);