2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/mutex.h>
40 #include <sys/sched.h>
43 #include <sys/malloc.h>
46 #include <vm/vm_extern.h>
47 #include <vm/vm_kern.h>
50 #include <machine/armreg.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/debug_monitor.h>
54 #include <machine/smp.h>
55 #include <machine/pcb.h>
56 #include <machine/intr.h>
57 #include <machine/vmparam.h>
59 #include <machine/vfp.h>
62 #include <arm/mv/mvwin.h>
65 /* used to hold the AP's until we are ready to release them */
66 struct mtx ap_boot_mtx;
68 /* # of Applications processors */
71 /* Set to 1 once we're ready to let the APs out of the pen. */
72 volatile int aps_ready = 0;
74 void set_stackptrs(int cpu);
76 /* Temporary variables for init_secondary() */
77 void *dpcpu[MAXCPU - 1];
79 /* Determine if we running MP machine */
84 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
86 CPU_SETOF(0, &all_cpus);
88 return (mp_ncpus > 1);
91 /* Start Application Processor via platform specific function */
97 for (ms = 0; ms < 2000; ++ms) {
98 if ((mp_naps + 1) == mp_ncpus)
99 return (0); /* success */
107 /* Initialize and fire up non-boot processors */
113 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
115 /* Reserve memory for application processors */
116 for(i = 0; i < (mp_ncpus - 1); i++)
117 dpcpu[i] = kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
119 dcache_wbinv_poc_all();
121 /* Initialize boot code and start up processors */
122 platform_mp_start_ap();
124 /* Check if ap's started properly */
127 printf("WARNING: Some AP's failed to start\n");
129 for (i = 1; i < mp_ncpus; i++)
130 CPU_SET(i, &all_cpus);
133 /* Introduce rest of cores to the world */
135 cpu_mp_announce(void)
141 init_secondary(int cpu)
144 uint32_t loop_counter;
147 cpuinfo_reinit_mmu(pmap_kern_ttb);
150 /* Provide stack pointers for other processor modes. */
153 enable_interrupts(PSR_A);
157 * pcpu_init() updates queue, so it should not be executed in parallel
160 while(mp_naps < (cpu - 1))
163 pcpu_init(pc, cpu, sizeof(struct pcpu));
164 pc->pc_mpidr = cp15_mpidr_get() & 0xFFFFFF;
165 dpcpu_init(dpcpu[cpu - 1], cpu);
167 dbg_monitor_init_secondary();
169 /* Signal our startup to BSP */
170 atomic_add_rel_32(&mp_naps, 1);
172 /* Spin until the BSP releases the APs */
173 while (!atomic_load_acq_int(&aps_ready)) {
175 __asm __volatile("wfe");
179 /* Initialize curthread */
180 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
181 pc->pc_curthread = pc->pc_idlethread;
182 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
183 set_curthread(pc->pc_idlethread);
189 /* Configure the interrupt controller */
190 intr_pic_init_secondary();
192 /* Apply possible BP hardening */
193 cpuinfo_init_bp_hardening();
195 mtx_lock_spin(&ap_boot_mtx);
197 atomic_add_rel_32(&smp_cpus, 1);
199 if (smp_cpus == mp_ncpus) {
200 /* enable IPI's, tlb shootdown, freezes etc */
201 atomic_store_rel_int(&smp_started, 1);
204 mtx_unlock_spin(&ap_boot_mtx);
207 while (smp_started == 0) {
210 if (loop_counter == 1000)
211 CTR0(KTR_SMP, "AP still wait for smp_started");
213 /* Start per-CPU event timers. */
216 CTR0(KTR_SMP, "go into scheduler");
218 /* Enter the scheduler */
221 panic("scheduler returned us to %s", __func__);
226 ipi_rendezvous(void *dummy __unused)
229 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
230 smp_rendezvous_action();
234 ipi_ast(void *dummy __unused)
237 CTR0(KTR_SMP, "IPI_AST");
241 ipi_stop(void *dummy __unused)
246 * IPI_STOP_HARD is mapped to IPI_STOP.
248 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
250 cpu = PCPU_GET(cpuid);
251 savectx(&stoppcbs[cpu]);
254 * CPUs are stopped when entering the debugger and at
255 * system shutdown, both events which can precede a
256 * panic dump. For the dump to be correct, all caches
257 * must be flushed and invalidated, but on ARM there's
258 * no way to broadcast a wbinv_all to other cores.
259 * Instead, we have each core do the local wbinv_all as
260 * part of stopping the core. The core requesting the
261 * stop will do the l2 cache flush after all other cores
262 * have done their l1 flushes and stopped.
264 dcache_wbinv_poc_all();
266 /* Indicate we are stopped */
267 CPU_SET_ATOMIC(cpu, &stopped_cpus);
269 /* Wait for restart */
270 while (!CPU_ISSET(cpu, &started_cpus))
273 CPU_CLR_ATOMIC(cpu, &started_cpus);
274 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
278 CTR0(KTR_SMP, "IPI_STOP (restart)");
282 ipi_preempt(void *arg)
285 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
286 sched_preempt(curthread);
290 ipi_hardclock(void *arg)
293 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
298 release_aps(void *dummy __unused)
300 uint32_t loop_counter;
305 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
306 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
307 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
308 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
309 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
311 atomic_store_rel_int(&aps_ready, 1);
312 /* Wake the other threads up */
316 printf("Release APs\n");
318 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
323 printf("AP's not started\n");
326 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
332 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
336 cpu_mp_setmaxid(void)
339 platform_mp_setmaxid();
344 ipi_all_but_self(u_int ipi)
348 other_cpus = all_cpus;
349 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
350 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
351 intr_ipi_send(other_cpus, ipi);
355 ipi_cpu(int cpu, u_int ipi)
362 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
363 intr_ipi_send(cpus, ipi);
367 ipi_selected(cpuset_t cpus, u_int ipi)
370 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
371 intr_ipi_send(cpus, ipi);