2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/mutex.h>
40 #include <sys/sched.h>
43 #include <sys/malloc.h>
46 #include <vm/vm_extern.h>
47 #include <vm/vm_kern.h>
50 #include <machine/armreg.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/debug_monitor.h>
54 #include <machine/smp.h>
55 #include <machine/pcb.h>
56 #include <machine/intr.h>
57 #include <machine/vmparam.h>
59 #include <machine/vfp.h>
62 #include <arm/mv/mvwin.h>
65 /* used to hold the AP's until we are ready to release them */
66 struct mtx ap_boot_mtx;
67 struct pcb stoppcbs[MAXCPU];
69 /* # of Applications processors */
72 /* Set to 1 once we're ready to let the APs out of the pen. */
73 volatile int aps_ready = 0;
75 void set_stackptrs(int cpu);
77 /* Temporary variables for init_secondary() */
78 void *dpcpu[MAXCPU - 1];
80 /* Determine if we running MP machine */
85 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
87 CPU_SETOF(0, &all_cpus);
89 return (mp_ncpus > 1);
92 /* Start Application Processor via platform specific function */
98 for (ms = 0; ms < 2000; ++ms) {
99 if ((mp_naps + 1) == mp_ncpus)
100 return (0); /* success */
108 /* Initialize and fire up non-boot processors */
114 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
116 /* Reserve memory for application processors */
117 for(i = 0; i < (mp_ncpus - 1); i++)
118 dpcpu[i] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
120 dcache_wbinv_poc_all();
122 /* Initialize boot code and start up processors */
123 platform_mp_start_ap();
125 /* Check if ap's started properly */
128 printf("WARNING: Some AP's failed to start\n");
130 for (i = 1; i < mp_ncpus; i++)
131 CPU_SET(i, &all_cpus);
134 /* Introduce rest of cores to the world */
136 cpu_mp_announce(void)
142 init_secondary(int cpu)
145 uint32_t loop_counter;
148 cpuinfo_reinit_mmu(pmap_kern_ttb);
151 /* Provide stack pointers for other processor modes. */
154 enable_interrupts(PSR_A);
158 * pcpu_init() updates queue, so it should not be executed in parallel
161 while(mp_naps < (cpu - 1))
164 pcpu_init(pc, cpu, sizeof(struct pcpu));
165 pc->pc_mpidr = cp15_mpidr_get() & 0xFFFFFF;
166 dpcpu_init(dpcpu[cpu - 1], cpu);
168 dbg_monitor_init_secondary();
170 /* Signal our startup to BSP */
171 atomic_add_rel_32(&mp_naps, 1);
173 /* Spin until the BSP releases the APs */
174 while (!atomic_load_acq_int(&aps_ready)) {
176 __asm __volatile("wfe");
180 /* Initialize curthread */
181 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
182 pc->pc_curthread = pc->pc_idlethread;
183 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
184 set_curthread(pc->pc_idlethread);
190 /* Configure the interrupt controller */
191 intr_pic_init_secondary();
193 /* Apply possible BP hardening */
194 cpuinfo_init_bp_hardening();
196 mtx_lock_spin(&ap_boot_mtx);
198 atomic_add_rel_32(&smp_cpus, 1);
200 if (smp_cpus == mp_ncpus) {
201 /* enable IPI's, tlb shootdown, freezes etc */
202 atomic_store_rel_int(&smp_started, 1);
205 mtx_unlock_spin(&ap_boot_mtx);
208 while (smp_started == 0) {
211 if (loop_counter == 1000)
212 CTR0(KTR_SMP, "AP still wait for smp_started");
214 /* Start per-CPU event timers. */
217 CTR0(KTR_SMP, "go into scheduler");
219 /* Enter the scheduler */
222 panic("scheduler returned us to %s", __func__);
227 ipi_rendezvous(void *dummy __unused)
230 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
231 smp_rendezvous_action();
235 ipi_ast(void *dummy __unused)
238 CTR0(KTR_SMP, "IPI_AST");
242 ipi_stop(void *dummy __unused)
247 * IPI_STOP_HARD is mapped to IPI_STOP.
249 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
251 cpu = PCPU_GET(cpuid);
252 savectx(&stoppcbs[cpu]);
255 * CPUs are stopped when entering the debugger and at
256 * system shutdown, both events which can precede a
257 * panic dump. For the dump to be correct, all caches
258 * must be flushed and invalidated, but on ARM there's
259 * no way to broadcast a wbinv_all to other cores.
260 * Instead, we have each core do the local wbinv_all as
261 * part of stopping the core. The core requesting the
262 * stop will do the l2 cache flush after all other cores
263 * have done their l1 flushes and stopped.
265 dcache_wbinv_poc_all();
267 /* Indicate we are stopped */
268 CPU_SET_ATOMIC(cpu, &stopped_cpus);
270 /* Wait for restart */
271 while (!CPU_ISSET(cpu, &started_cpus))
274 CPU_CLR_ATOMIC(cpu, &started_cpus);
275 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
279 CTR0(KTR_SMP, "IPI_STOP (restart)");
283 ipi_preempt(void *arg)
285 struct trapframe *oldframe;
290 td->td_intr_nesting_level++;
291 oldframe = td->td_intr_frame;
292 td->td_intr_frame = (struct trapframe *)arg;
294 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
297 td->td_intr_frame = oldframe;
298 td->td_intr_nesting_level--;
303 ipi_hardclock(void *arg)
305 struct trapframe *oldframe;
310 td->td_intr_nesting_level++;
311 oldframe = td->td_intr_frame;
312 td->td_intr_frame = (struct trapframe *)arg;
314 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
317 td->td_intr_frame = oldframe;
318 td->td_intr_nesting_level--;
323 release_aps(void *dummy __unused)
325 uint32_t loop_counter;
330 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
331 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
332 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
333 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
334 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
336 atomic_store_rel_int(&aps_ready, 1);
337 /* Wake the other threads up */
341 printf("Release APs\n");
343 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
348 printf("AP's not started\n");
351 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
357 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
361 cpu_mp_setmaxid(void)
364 platform_mp_setmaxid();
369 ipi_all_but_self(u_int ipi)
373 other_cpus = all_cpus;
374 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
375 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
376 intr_ipi_send(other_cpus, ipi);
380 ipi_cpu(int cpu, u_int ipi)
387 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
388 intr_ipi_send(cpus, ipi);
392 ipi_selected(cpuset_t cpus, u_int ipi)
395 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
396 intr_ipi_send(cpus, ipi);