2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/mutex.h>
39 #include <sys/sched.h>
42 #include <sys/malloc.h>
45 #include <vm/vm_extern.h>
46 #include <vm/vm_kern.h>
49 #include <machine/armreg.h>
50 #include <machine/cpu.h>
51 #include <machine/cpufunc.h>
52 #include <machine/debug_monitor.h>
53 #include <machine/smp.h>
54 #include <machine/pcb.h>
55 #include <machine/physmem.h>
56 #include <machine/intr.h>
57 #include <machine/vmparam.h>
59 #include <machine/vfp.h>
62 #include <arm/mv/mvwin.h>
65 extern struct pcpu __pcpu[];
66 /* used to hold the AP's until we are ready to release them */
67 struct mtx ap_boot_mtx;
68 struct pcb stoppcbs[MAXCPU];
70 /* # of Applications processors */
73 /* Set to 1 once we're ready to let the APs out of the pen. */
74 volatile int aps_ready = 0;
77 static int ipi_handler(void *arg);
79 void set_stackptrs(int cpu);
81 /* Temporary variables for init_secondary() */
82 void *dpcpu[MAXCPU - 1];
84 /* Determine if we running MP machine */
89 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
91 CPU_SETOF(0, &all_cpus);
93 return (mp_ncpus > 1);
96 /* Start Application Processor via platform specific function */
102 for (ms = 0; ms < 2000; ++ms) {
103 if ((mp_naps + 1) == mp_ncpus)
104 return (0); /* success */
112 extern unsigned char _end[];
114 /* Initialize and fire up non-boot processors */
120 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
122 /* Reserve memory for application processors */
123 for(i = 0; i < (mp_ncpus - 1); i++)
124 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
127 dcache_wbinv_poc_all();
129 /* Initialize boot code and start up processors */
130 platform_mp_start_ap();
132 /* Check if ap's started properly */
135 printf("WARNING: Some AP's failed to start\n");
137 for (i = 1; i < mp_ncpus; i++)
138 CPU_SET(i, &all_cpus);
141 /* Introduce rest of cores to the world */
143 cpu_mp_announce(void)
148 extern vm_paddr_t pmap_pa;
150 init_secondary(int cpu)
153 uint32_t loop_counter;
155 int start = 0, end = 0;
157 uint32_t actlr_mask, actlr_set;
160 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
161 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
164 /* Provide stack pointers for other processor modes. */
167 enable_interrupts(PSR_A);
171 * pcpu_init() updates queue, so it should not be executed in parallel
174 while(mp_naps < (cpu - 1))
177 pcpu_init(pc, cpu, sizeof(struct pcpu));
178 dpcpu_init(dpcpu[cpu - 1], cpu);
179 #if __ARM_ARCH >= 6 && defined(DDB)
180 dbg_monitor_init_secondary();
182 /* Signal our startup to BSP */
183 atomic_add_rel_32(&mp_naps, 1);
185 /* Spin until the BSP releases the APs */
186 while (!atomic_load_acq_int(&aps_ready)) {
188 __asm __volatile("wfe");
192 /* Initialize curthread */
193 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
194 pc->pc_curthread = pc->pc_idlethread;
195 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
196 set_curthread(pc->pc_idlethread);
201 /* Configure the interrupt controller */
202 intr_pic_init_secondary();
204 mtx_lock_spin(&ap_boot_mtx);
206 atomic_add_rel_32(&smp_cpus, 1);
208 if (smp_cpus == mp_ncpus) {
209 /* enable IPI's, tlb shootdown, freezes etc */
210 atomic_store_rel_int(&smp_started, 1);
213 mtx_unlock_spin(&ap_boot_mtx);
218 start = IPI_IRQ_START;
226 for (int i = start; i <= end; i++)
229 enable_interrupts(PSR_I);
232 while (smp_started == 0) {
235 if (loop_counter == 1000)
236 CTR0(KTR_SMP, "AP still wait for smp_started");
238 /* Start per-CPU event timers. */
241 CTR0(KTR_SMP, "go into scheduler");
243 /* Enter the scheduler */
246 panic("scheduler returned us to %s", __func__);
252 ipi_rendezvous(void *dummy __unused)
255 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
256 smp_rendezvous_action();
260 ipi_ast(void *dummy __unused)
263 CTR0(KTR_SMP, "IPI_AST");
267 ipi_stop(void *dummy __unused)
272 * IPI_STOP_HARD is mapped to IPI_STOP.
274 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
276 cpu = PCPU_GET(cpuid);
277 savectx(&stoppcbs[cpu]);
280 * CPUs are stopped when entering the debugger and at
281 * system shutdown, both events which can precede a
282 * panic dump. For the dump to be correct, all caches
283 * must be flushed and invalidated, but on ARM there's
284 * no way to broadcast a wbinv_all to other cores.
285 * Instead, we have each core do the local wbinv_all as
286 * part of stopping the core. The core requesting the
287 * stop will do the l2 cache flush after all other cores
288 * have done their l1 flushes and stopped.
290 dcache_wbinv_poc_all();
292 /* Indicate we are stopped */
293 CPU_SET_ATOMIC(cpu, &stopped_cpus);
295 /* Wait for restart */
296 while (!CPU_ISSET(cpu, &started_cpus))
299 CPU_CLR_ATOMIC(cpu, &started_cpus);
300 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
304 CTR0(KTR_SMP, "IPI_STOP (restart)");
308 ipi_preempt(void *arg)
310 struct trapframe *oldframe;
315 td->td_intr_nesting_level++;
316 oldframe = td->td_intr_frame;
317 td->td_intr_frame = (struct trapframe *)arg;
319 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
322 td->td_intr_frame = oldframe;
323 td->td_intr_nesting_level--;
328 ipi_hardclock(void *arg)
330 struct trapframe *oldframe;
335 td->td_intr_nesting_level++;
336 oldframe = td->td_intr_frame;
337 td->td_intr_frame = (struct trapframe *)arg;
339 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
342 td->td_intr_frame = oldframe;
343 td->td_intr_nesting_level--;
349 ipi_handler(void *arg)
353 cpu = PCPU_GET(cpuid);
355 ipi = pic_ipi_read((int)arg);
357 while ((ipi != 0x3ff)) {
360 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
361 smp_rendezvous_action();
365 CTR0(KTR_SMP, "IPI_AST");
370 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
371 * necessary to add it in the switch.
373 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
375 savectx(&stoppcbs[cpu]);
378 * CPUs are stopped when entering the debugger and at
379 * system shutdown, both events which can precede a
380 * panic dump. For the dump to be correct, all caches
381 * must be flushed and invalidated, but on ARM there's
382 * no way to broadcast a wbinv_all to other cores.
383 * Instead, we have each core do the local wbinv_all as
384 * part of stopping the core. The core requesting the
385 * stop will do the l2 cache flush after all other cores
386 * have done their l1 flushes and stopped.
388 dcache_wbinv_poc_all();
390 /* Indicate we are stopped */
391 CPU_SET_ATOMIC(cpu, &stopped_cpus);
393 /* Wait for restart */
394 while (!CPU_ISSET(cpu, &started_cpus))
397 CPU_CLR_ATOMIC(cpu, &started_cpus);
398 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
402 CTR0(KTR_SMP, "IPI_STOP (restart)");
405 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
406 sched_preempt(curthread);
409 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
413 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
417 ipi = pic_ipi_read(-1);
420 return (FILTER_HANDLED);
425 release_aps(void *dummy __unused)
427 uint32_t loop_counter;
429 int start = 0, end = 0;
436 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
437 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
438 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
439 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
440 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
443 start = IPI_IRQ_START;
451 for (int i = start; i <= end; i++) {
456 * Use 0xdeadbeef as the argument value for irq 0,
457 * if we used 0, the intr code will give the trap frame
460 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
461 INTR_TYPE_MISC | INTR_EXCL, NULL);
467 atomic_store_rel_int(&aps_ready, 1);
468 /* Wake the other threads up */
472 printf("Release APs\n");
474 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
479 printf("AP's not started\n");
482 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
488 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
492 cpu_mp_setmaxid(void)
495 platform_mp_setmaxid();
500 ipi_all_but_self(u_int ipi)
504 other_cpus = all_cpus;
505 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
506 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
508 intr_ipi_send(other_cpus, ipi);
510 pic_ipi_send(other_cpus, ipi);
515 ipi_cpu(int cpu, u_int ipi)
522 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
524 intr_ipi_send(cpus, ipi);
526 pic_ipi_send(cpus, ipi);
531 ipi_selected(cpuset_t cpus, u_int ipi)
534 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
536 intr_ipi_send(cpus, ipi);
538 pic_ipi_send(cpus, ipi);