2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/mutex.h>
39 #include <sys/sched.h>
42 #include <sys/malloc.h>
45 #include <vm/vm_extern.h>
46 #include <vm/vm_kern.h>
49 #include <machine/armreg.h>
50 #include <machine/cpu.h>
51 #include <machine/cpufunc.h>
52 #include <machine/debug_monitor.h>
53 #include <machine/smp.h>
54 #include <machine/pcb.h>
55 #include <machine/physmem.h>
56 #include <machine/intr.h>
57 #include <machine/vmparam.h>
59 #include <machine/vfp.h>
62 #include <arm/mv/mvwin.h>
65 extern struct pcpu __pcpu[];
66 /* used to hold the AP's until we are ready to release them */
67 struct mtx ap_boot_mtx;
68 struct pcb stoppcbs[MAXCPU];
70 /* # of Applications processors */
73 /* Set to 1 once we're ready to let the APs out of the pen. */
74 volatile int aps_ready = 0;
77 static int ipi_handler(void *arg);
79 void set_stackptrs(int cpu);
81 /* Temporary variables for init_secondary() */
82 void *dpcpu[MAXCPU - 1];
84 /* Determine if we running MP machine */
89 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset"));
91 CPU_SETOF(0, &all_cpus);
93 return (mp_ncpus > 1);
96 /* Start Application Processor via platform specific function */
102 for (ms = 0; ms < 2000; ++ms) {
103 if ((mp_naps + 1) == mp_ncpus)
104 return (0); /* success */
112 extern unsigned char _end[];
114 /* Initialize and fire up non-boot processors */
120 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
122 /* Reserve memory for application processors */
123 for(i = 0; i < (mp_ncpus - 1); i++)
124 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
127 dcache_wbinv_poc_all();
129 /* Initialize boot code and start up processors */
130 platform_mp_start_ap();
132 /* Check if ap's started properly */
135 printf("WARNING: Some AP's failed to start\n");
137 for (i = 1; i < mp_ncpus; i++)
138 CPU_SET(i, &all_cpus);
141 /* Introduce rest of cores to the world */
143 cpu_mp_announce(void)
148 extern vm_paddr_t pmap_pa;
150 init_secondary(int cpu)
153 uint32_t loop_counter;
155 int start = 0, end = 0;
159 cpuinfo_reinit_mmu(pmap_kern_ttb);
162 /* Provide stack pointers for other processor modes. */
165 enable_interrupts(PSR_A);
169 * pcpu_init() updates queue, so it should not be executed in parallel
172 while(mp_naps < (cpu - 1))
175 pcpu_init(pc, cpu, sizeof(struct pcpu));
176 dpcpu_init(dpcpu[cpu - 1], cpu);
177 #if __ARM_ARCH >= 6 && defined(DDB)
178 dbg_monitor_init_secondary();
180 /* Signal our startup to BSP */
181 atomic_add_rel_32(&mp_naps, 1);
183 /* Spin until the BSP releases the APs */
184 while (!atomic_load_acq_int(&aps_ready)) {
186 __asm __volatile("wfe");
190 /* Initialize curthread */
191 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
192 pc->pc_curthread = pc->pc_idlethread;
193 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
194 set_curthread(pc->pc_idlethread);
199 /* Configure the interrupt controller */
200 intr_pic_init_secondary();
202 mtx_lock_spin(&ap_boot_mtx);
204 atomic_add_rel_32(&smp_cpus, 1);
206 if (smp_cpus == mp_ncpus) {
207 /* enable IPI's, tlb shootdown, freezes etc */
208 atomic_store_rel_int(&smp_started, 1);
211 mtx_unlock_spin(&ap_boot_mtx);
216 start = IPI_IRQ_START;
224 for (int i = start; i <= end; i++)
227 enable_interrupts(PSR_I);
230 while (smp_started == 0) {
233 if (loop_counter == 1000)
234 CTR0(KTR_SMP, "AP still wait for smp_started");
236 /* Start per-CPU event timers. */
239 CTR0(KTR_SMP, "go into scheduler");
241 /* Enter the scheduler */
244 panic("scheduler returned us to %s", __func__);
250 ipi_rendezvous(void *dummy __unused)
253 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
254 smp_rendezvous_action();
258 ipi_ast(void *dummy __unused)
261 CTR0(KTR_SMP, "IPI_AST");
265 ipi_stop(void *dummy __unused)
270 * IPI_STOP_HARD is mapped to IPI_STOP.
272 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
274 cpu = PCPU_GET(cpuid);
275 savectx(&stoppcbs[cpu]);
278 * CPUs are stopped when entering the debugger and at
279 * system shutdown, both events which can precede a
280 * panic dump. For the dump to be correct, all caches
281 * must be flushed and invalidated, but on ARM there's
282 * no way to broadcast a wbinv_all to other cores.
283 * Instead, we have each core do the local wbinv_all as
284 * part of stopping the core. The core requesting the
285 * stop will do the l2 cache flush after all other cores
286 * have done their l1 flushes and stopped.
288 dcache_wbinv_poc_all();
290 /* Indicate we are stopped */
291 CPU_SET_ATOMIC(cpu, &stopped_cpus);
293 /* Wait for restart */
294 while (!CPU_ISSET(cpu, &started_cpus))
297 CPU_CLR_ATOMIC(cpu, &started_cpus);
298 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
302 CTR0(KTR_SMP, "IPI_STOP (restart)");
306 ipi_preempt(void *arg)
308 struct trapframe *oldframe;
313 td->td_intr_nesting_level++;
314 oldframe = td->td_intr_frame;
315 td->td_intr_frame = (struct trapframe *)arg;
317 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
320 td->td_intr_frame = oldframe;
321 td->td_intr_nesting_level--;
326 ipi_hardclock(void *arg)
328 struct trapframe *oldframe;
333 td->td_intr_nesting_level++;
334 oldframe = td->td_intr_frame;
335 td->td_intr_frame = (struct trapframe *)arg;
337 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
340 td->td_intr_frame = oldframe;
341 td->td_intr_nesting_level--;
347 ipi_handler(void *arg)
351 cpu = PCPU_GET(cpuid);
353 ipi = pic_ipi_read((int)arg);
355 while ((ipi != 0x3ff)) {
358 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
359 smp_rendezvous_action();
363 CTR0(KTR_SMP, "IPI_AST");
368 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
369 * necessary to add it in the switch.
371 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
373 savectx(&stoppcbs[cpu]);
376 * CPUs are stopped when entering the debugger and at
377 * system shutdown, both events which can precede a
378 * panic dump. For the dump to be correct, all caches
379 * must be flushed and invalidated, but on ARM there's
380 * no way to broadcast a wbinv_all to other cores.
381 * Instead, we have each core do the local wbinv_all as
382 * part of stopping the core. The core requesting the
383 * stop will do the l2 cache flush after all other cores
384 * have done their l1 flushes and stopped.
386 dcache_wbinv_poc_all();
388 /* Indicate we are stopped */
389 CPU_SET_ATOMIC(cpu, &stopped_cpus);
391 /* Wait for restart */
392 while (!CPU_ISSET(cpu, &started_cpus))
395 CPU_CLR_ATOMIC(cpu, &started_cpus);
396 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
400 CTR0(KTR_SMP, "IPI_STOP (restart)");
403 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
404 sched_preempt(curthread);
407 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
411 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
415 ipi = pic_ipi_read(-1);
418 return (FILTER_HANDLED);
423 release_aps(void *dummy __unused)
425 uint32_t loop_counter;
427 int start = 0, end = 0;
434 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
435 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
436 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
437 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
438 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
441 start = IPI_IRQ_START;
449 for (int i = start; i <= end; i++) {
454 * Use 0xdeadbeef as the argument value for irq 0,
455 * if we used 0, the intr code will give the trap frame
458 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
459 INTR_TYPE_MISC | INTR_EXCL, NULL);
465 atomic_store_rel_int(&aps_ready, 1);
466 /* Wake the other threads up */
470 printf("Release APs\n");
472 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
477 printf("AP's not started\n");
480 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
486 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
490 cpu_mp_setmaxid(void)
493 platform_mp_setmaxid();
498 ipi_all_but_self(u_int ipi)
502 other_cpus = all_cpus;
503 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
504 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
506 intr_ipi_send(other_cpus, ipi);
508 pic_ipi_send(other_cpus, ipi);
513 ipi_cpu(int cpu, u_int ipi)
520 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
522 intr_ipi_send(cpus, ipi);
524 pic_ipi_send(cpus, ipi);
529 ipi_selected(cpuset_t cpus, u_int ipi)
532 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
534 intr_ipi_send(cpus, ipi);
536 pic_ipi_send(cpus, ipi);