2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
31 #include <sys/kernel.h>
33 #include <sys/mutex.h>
36 #include <sys/sched.h>
39 #include <sys/malloc.h>
42 #include <vm/vm_extern.h>
43 #include <vm/vm_kern.h>
46 #include <machine/acle-compat.h>
47 #include <machine/armreg.h>
48 #include <machine/cpu.h>
49 #include <machine/cpufunc.h>
50 #include <machine/debug_monitor.h>
51 #include <machine/smp.h>
52 #include <machine/pcb.h>
53 #include <machine/pmap.h>
54 #include <machine/physmem.h>
55 #include <machine/intr.h>
56 #include <machine/vmparam.h>
58 #include <machine/vfp.h>
61 #include <arm/mv/mvwin.h>
62 #include <dev/fdt/fdt_common.h>
67 extern struct pcpu __pcpu[];
68 /* used to hold the AP's until we are ready to release them */
69 struct mtx ap_boot_mtx;
70 struct pcb stoppcbs[MAXCPU];
72 /* # of Applications processors */
75 /* Set to 1 once we're ready to let the APs out of the pen. */
76 volatile int aps_ready = 0;
79 static int ipi_handler(void *arg);
81 void set_stackptrs(int cpu);
83 /* Temporary variables for init_secondary() */
84 void *dpcpu[MAXCPU - 1];
86 /* Determine if we running MP machine */
90 CPU_SETOF(0, &all_cpus);
92 return (platform_mp_probe());
95 /* Start Application Processor via platform specific function */
101 for (ms = 0; ms < 2000; ++ms) {
102 if ((mp_naps + 1) == mp_ncpus)
103 return (0); /* success */
111 extern unsigned char _end[];
113 /* Initialize and fire up non-boot processors */
119 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
121 /* Reserve memory for application processors */
122 for(i = 0; i < (mp_ncpus - 1); i++)
123 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
126 dcache_wbinv_poc_all();
128 /* Initialize boot code and start up processors */
129 platform_mp_start_ap();
131 /* Check if ap's started properly */
134 printf("WARNING: Some AP's failed to start\n");
136 for (i = 1; i < mp_ncpus; i++)
137 CPU_SET(i, &all_cpus);
140 /* Introduce rest of cores to the world */
142 cpu_mp_announce(void)
147 extern vm_paddr_t pmap_pa;
149 init_secondary(int cpu)
152 uint32_t loop_counter;
154 int start = 0, end = 0;
156 uint32_t actlr_mask, actlr_set;
159 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
160 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
163 /* Provide stack pointers for other processor modes. */
166 enable_interrupts(PSR_A);
170 * pcpu_init() updates queue, so it should not be executed in parallel
173 while(mp_naps < (cpu - 1))
176 pcpu_init(pc, cpu, sizeof(struct pcpu));
177 dpcpu_init(dpcpu[cpu - 1], cpu);
178 /* Signal our startup to BSP */
179 atomic_add_rel_32(&mp_naps, 1);
181 /* Spin until the BSP releases the APs */
182 while (!atomic_load_acq_int(&aps_ready)) {
184 __asm __volatile("wfe");
188 /* Initialize curthread */
189 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
190 pc->pc_curthread = pc->pc_idlethread;
191 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
192 set_curthread(pc->pc_idlethread);
197 mtx_lock_spin(&ap_boot_mtx);
199 atomic_add_rel_32(&smp_cpus, 1);
201 if (smp_cpus == mp_ncpus) {
202 /* enable IPI's, tlb shootdown, freezes etc */
203 atomic_store_rel_int(&smp_started, 1);
206 mtx_unlock_spin(&ap_boot_mtx);
211 start = IPI_IRQ_START;
219 for (int i = start; i <= end; i++)
222 enable_interrupts(PSR_I);
225 while (smp_started == 0) {
228 if (loop_counter == 1000)
229 CTR0(KTR_SMP, "AP still wait for smp_started");
231 /* Start per-CPU event timers. */
234 CTR0(KTR_SMP, "go into scheduler");
235 platform_mp_init_secondary();
237 /* Enter the scheduler */
240 panic("scheduler returned us to %s", __func__);
246 ipi_rendezvous(void *dummy __unused)
249 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
250 smp_rendezvous_action();
254 ipi_ast(void *dummy __unused)
257 CTR0(KTR_SMP, "IPI_AST");
261 ipi_stop(void *dummy __unused)
266 * IPI_STOP_HARD is mapped to IPI_STOP.
268 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
270 cpu = PCPU_GET(cpuid);
271 savectx(&stoppcbs[cpu]);
274 * CPUs are stopped when entering the debugger and at
275 * system shutdown, both events which can precede a
276 * panic dump. For the dump to be correct, all caches
277 * must be flushed and invalidated, but on ARM there's
278 * no way to broadcast a wbinv_all to other cores.
279 * Instead, we have each core do the local wbinv_all as
280 * part of stopping the core. The core requesting the
281 * stop will do the l2 cache flush after all other cores
282 * have done their l1 flushes and stopped.
284 dcache_wbinv_poc_all();
286 /* Indicate we are stopped */
287 CPU_SET_ATOMIC(cpu, &stopped_cpus);
289 /* Wait for restart */
290 while (!CPU_ISSET(cpu, &started_cpus))
293 CPU_CLR_ATOMIC(cpu, &started_cpus);
294 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
298 CTR0(KTR_SMP, "IPI_STOP (restart)");
302 ipi_preempt(void *arg)
304 struct trapframe *oldframe;
309 td->td_intr_nesting_level++;
310 oldframe = td->td_intr_frame;
311 td->td_intr_frame = (struct trapframe *)arg;
313 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
316 td->td_intr_frame = oldframe;
317 td->td_intr_nesting_level--;
322 ipi_hardclock(void *arg)
324 struct trapframe *oldframe;
329 td->td_intr_nesting_level++;
330 oldframe = td->td_intr_frame;
331 td->td_intr_frame = (struct trapframe *)arg;
333 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
336 td->td_intr_frame = oldframe;
337 td->td_intr_nesting_level--;
343 ipi_handler(void *arg)
347 cpu = PCPU_GET(cpuid);
349 ipi = pic_ipi_read((int)arg);
351 while ((ipi != 0x3ff)) {
354 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
355 smp_rendezvous_action();
359 CTR0(KTR_SMP, "IPI_AST");
364 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
365 * necessary to add it in the switch.
367 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
369 savectx(&stoppcbs[cpu]);
372 * CPUs are stopped when entering the debugger and at
373 * system shutdown, both events which can precede a
374 * panic dump. For the dump to be correct, all caches
375 * must be flushed and invalidated, but on ARM there's
376 * no way to broadcast a wbinv_all to other cores.
377 * Instead, we have each core do the local wbinv_all as
378 * part of stopping the core. The core requesting the
379 * stop will do the l2 cache flush after all other cores
380 * have done their l1 flushes and stopped.
382 dcache_wbinv_poc_all();
384 /* Indicate we are stopped */
385 CPU_SET_ATOMIC(cpu, &stopped_cpus);
387 /* Wait for restart */
388 while (!CPU_ISSET(cpu, &started_cpus))
391 CPU_CLR_ATOMIC(cpu, &started_cpus);
392 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
396 CTR0(KTR_SMP, "IPI_STOP (restart)");
399 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
400 sched_preempt(curthread);
403 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
407 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
411 ipi = pic_ipi_read(-1);
414 return (FILTER_HANDLED);
419 release_aps(void *dummy __unused)
421 uint32_t loop_counter;
423 int start = 0, end = 0;
430 intr_ipi_set_handler(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL, 0);
431 intr_ipi_set_handler(IPI_AST, "ast", ipi_ast, NULL, 0);
432 intr_ipi_set_handler(IPI_STOP, "stop", ipi_stop, NULL, 0);
433 intr_ipi_set_handler(IPI_PREEMPT, "preempt", ipi_preempt, NULL, 0);
434 intr_ipi_set_handler(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL, 0);
438 start = IPI_IRQ_START;
446 for (int i = start; i <= end; i++) {
451 * Use 0xdeadbeef as the argument value for irq 0,
452 * if we used 0, the intr code will give the trap frame
455 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
456 INTR_TYPE_MISC | INTR_EXCL, NULL);
462 atomic_store_rel_int(&aps_ready, 1);
463 /* Wake the other threads up */
468 printf("Release APs\n");
470 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
475 printf("AP's not started\n");
478 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
484 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
488 cpu_mp_setmaxid(void)
491 platform_mp_setmaxid();
496 ipi_all_but_self(u_int ipi)
500 other_cpus = all_cpus;
501 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
502 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
503 platform_ipi_send(other_cpus, ipi);
507 ipi_cpu(int cpu, u_int ipi)
514 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
515 platform_ipi_send(cpus, ipi);
519 ipi_selected(cpuset_t cpus, u_int ipi)
522 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
523 platform_ipi_send(cpus, ipi);