2 * Copyright (c) 2011 The FreeBSD Foundation
5 * Developed by Ben Gray <ben.r.gray@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company nor the name of the author may be used to
16 * endorse or promote products derived from this software without specific
17 * prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * The ARM Cortex-A9 core can support a global timer plus a private and
34 * watchdog timer per core. This driver reserves memory and interrupt
35 * resources for accessing both timer register sets, these resources are
36 * stored globally and used to setup the timecount and eventtimer.
38 * The timecount timer uses the global 64-bit counter, whereas the
39 * per-CPU eventtimer uses the private 32-bit counters.
42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
45 #include <sys/cdefs.h>
46 __FBSDID("$FreeBSD$");
48 #include <sys/param.h>
49 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/malloc.h>
55 #include <sys/timeet.h>
56 #include <sys/timetc.h>
57 #include <sys/watchdog.h>
58 #include <machine/bus.h>
59 #include <machine/cpu.h>
60 #include <machine/intr.h>
62 #include <dev/fdt/fdt_common.h>
63 #include <dev/ofw/openfirm.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
67 #include <machine/bus.h>
68 #include <machine/fdt.h>
70 #include <arm/arm/mpcore_timervar.h>
72 /* Private (per-CPU) timer register map */
73 #define PRV_TIMER_LOAD 0x0000
74 #define PRV_TIMER_COUNT 0x0004
75 #define PRV_TIMER_CTRL 0x0008
76 #define PRV_TIMER_INTR 0x000C
78 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8
79 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
80 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1)
81 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
83 #define PRV_TIMER_INTR_EVENT (1UL << 0)
85 /* Global timer register map */
86 #define GBL_TIMER_COUNT_LOW 0x0000
87 #define GBL_TIMER_COUNT_HIGH 0x0004
88 #define GBL_TIMER_CTRL 0x0008
89 #define GBL_TIMER_INTR 0x000C
91 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8
92 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
93 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
94 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
95 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
97 #define GBL_TIMER_INTR_EVENT (1UL << 0)
99 struct arm_tmr_softc {
100 struct resource * tmr_res[4];
101 bus_space_tag_t prv_bst;
102 bus_space_tag_t gbl_bst;
103 bus_space_handle_t prv_bsh;
104 bus_space_handle_t gbl_bsh;
106 struct eventtimer et;
109 static struct resource_spec arm_tmr_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */
111 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */
112 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */
113 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */
117 static struct arm_tmr_softc *arm_tmr_sc = NULL;
119 static uint64_t platform_arm_tmr_freq = 0;
121 #define tmr_prv_read_4(reg) \
122 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg)
123 #define tmr_prv_write_4(reg, val) \
124 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val)
125 #define tmr_gbl_read_4(reg) \
126 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg)
127 #define tmr_gbl_write_4(reg, val) \
128 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val)
131 static timecounter_get_t arm_tmr_get_timecount;
133 static struct timecounter arm_tmr_timecount = {
135 .tc_get_timecount = arm_tmr_get_timecount,
137 .tc_counter_mask = ~0u,
143 * arm_tmr_get_timecount - reads the timecount (global) timer
144 * @tc: pointer to arm_tmr_timecount struct
146 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
147 * so (for now?) ignore the upper 32-bits.
150 * The lower 32-bits of the counter.
153 arm_tmr_get_timecount(struct timecounter *tc)
155 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW));
159 * arm_tmr_start - starts the eventtimer (private) timer
160 * @et: pointer to eventtimer struct
161 * @first: the number of seconds and fractional sections to trigger in
162 * @period: the period (in seconds and fractional sections) to set
164 * If the eventtimer is required to be in oneshot mode, period will be
165 * NULL and first will point to the time to trigger. If in periodic mode
166 * period will contain the time period and first may optionally contain
167 * the time for the first period.
173 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
175 uint32_t load, count;
178 tmr_prv_write_4(PRV_TIMER_CTRL, 0);
179 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
181 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
184 load = ((uint32_t)et->et_frequency * period) >> 32;
185 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
190 count = (uint32_t)((et->et_frequency * first) >> 32);
194 tmr_prv_write_4(PRV_TIMER_LOAD, load);
195 tmr_prv_write_4(PRV_TIMER_COUNT, count);
196 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl);
202 * arm_tmr_stop - stops the eventtimer (private) timer
203 * @et: pointer to eventtimer struct
205 * Simply stops the private timer by clearing all bits in the ctrl register.
211 arm_tmr_stop(struct eventtimer *et)
213 tmr_prv_write_4(PRV_TIMER_CTRL, 0);
214 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
219 * arm_tmr_intr - ISR for the eventtimer (private) timer
220 * @arg: pointer to arm_tmr_softc struct
222 * Clears the event register and then calls the eventtimer callback.
225 * Always returns FILTER_HANDLED
228 arm_tmr_intr(void *arg)
230 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg;
232 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
234 if (sc->et.et_active)
235 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
237 return (FILTER_HANDLED);
244 * arm_tmr_probe - timer probe routine
247 * The probe function returns success when probed with the fdt compatible
248 * string set to "arm,mpcore-timers".
251 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO.
254 arm_tmr_probe(device_t dev)
257 if (!ofw_bus_status_okay(dev))
260 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers"))
263 device_set_desc(dev, "ARM MPCore Timers");
264 return (BUS_PROBE_DEFAULT);
268 * arm_tmr_attach - attaches the timer to the simplebus
271 * Reserves memory and interrupt resources, stores the softc structure
272 * globally and registers both the timecount and eventtimer objects.
275 * Zero on sucess or ENXIO if an error occuried.
278 arm_tmr_attach(device_t dev)
280 struct arm_tmr_softc *sc = device_get_softc(dev);
284 boolean_t fixed_freq;
289 if (platform_arm_tmr_freq == ARM_TMR_FREQUENCY_VARIES) {
293 if (platform_arm_tmr_freq != 0) {
294 sc->clkfreq = platform_arm_tmr_freq;
296 /* Get the base clock frequency */
297 node = ofw_bus_get_node(dev);
298 if ((OF_getencprop(node, "clock-frequency", &clock,
299 sizeof(clock))) <= 0) {
300 device_printf(dev, "missing clock-frequency "
301 "attribute in FDT\n");
308 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
309 device_printf(dev, "could not allocate resources\n");
313 /* Global timer interface */
314 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]);
315 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]);
317 /* Private per-CPU timer interface */
318 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]);
319 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]);
323 /* Disable both timers to start off */
324 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000);
325 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000);
327 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr,
328 NULL, sc, &ihl) != 0) {
329 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res);
330 device_printf(dev, "Unable to setup the clock irq handler.\n");
335 * If the clock is fixed-frequency, setup and enable the global timer to
336 * use as the timecounter. If it's variable frequency it won't work as
337 * a timecounter. We also can't use it for DELAY(), so hopefully the
338 * platform provides its own implementation. If it doesn't, ours will
339 * get used, but since the frequency isn't set, it will only use the
340 * bogus loop counter.
343 tmr_gbl_write_4(GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
344 arm_tmr_timecount.tc_frequency = sc->clkfreq;
345 tc_init(&arm_tmr_timecount);
349 * Setup and register the eventtimer. Most event timers set their min
350 * and max period values to some value calculated from the clock
351 * frequency. We might not know yet what our runtime clock frequency
352 * will be, so we just use some safe values. A max of 2 seconds ensures
353 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
354 * we won't overflow our 32-bit timer count register. A min of 20
355 * nanoseconds is pretty much completely arbitrary.
357 sc->et.et_name = "MPCore";
358 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
359 sc->et.et_quality = 1000;
360 sc->et.et_frequency = sc->clkfreq;
361 sc->et.et_min_period = 20 * SBT_1NS;
362 sc->et.et_max_period = 2 * SBT_1S;
363 sc->et.et_start = arm_tmr_start;
364 sc->et.et_stop = arm_tmr_stop;
366 et_register(&sc->et);
371 static device_method_t arm_tmr_methods[] = {
372 DEVMETHOD(device_probe, arm_tmr_probe),
373 DEVMETHOD(device_attach, arm_tmr_attach),
377 static driver_t arm_tmr_driver = {
380 sizeof(struct arm_tmr_softc),
383 static devclass_t arm_tmr_devclass;
385 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
386 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
389 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
390 * frequency. When the CPU frequency changes due to power-saving or thermal
391 * managment, the platform-specific code that causes the frequency change calls
392 * this routine to inform the clock driver, and we in turn inform the event
393 * timer system, which actually updates the value in et->frequency for us and
394 * reschedules the current event(s) in a way that's atomic with respect to
395 * start/stop/intr code that may be running on various CPUs at the time of the
398 * This routine can also be called by a platform's early init code. If the
399 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
400 * to register as an eventtimer, but not a timecounter. If the value passed in
401 * is any other non-zero value it is used as the fixed frequency for the timer.
404 arm_tmr_change_frequency(uint64_t newfreq)
407 if (arm_tmr_sc == NULL)
408 platform_arm_tmr_freq = newfreq;
410 et_change_frequency(&arm_tmr_sc->et, newfreq);
414 * DELAY - Delay for at least usec microseconds.
415 * @usec: number of microseconds to delay by
417 * This function is called all over the kernel and is suppose to provide a
418 * consistent delay. This function may also be called before the console
419 * is setup so no printf's can be called here.
424 static void __used /* Must emit function code for the weak ref below. */
425 arm_tmr_DELAY(int usec)
427 int32_t counts_per_usec;
429 uint32_t first, last;
431 /* Check the timers are setup, if not just use a for loop for the meantime */
432 if (arm_tmr_sc == NULL || arm_tmr_timecount.tc_frequency == 0) {
433 for (; usec > 0; usec--)
434 for (counts = 200; counts > 0; counts--)
435 cpufunc_nullop(); /* Prevent gcc from optimizing
441 /* Get the number of times to count */
442 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
445 * Clamp the timeout at a maximum value (about 32 seconds with
446 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
447 * near that length of time and if they are, they should be hung
450 if (usec >= (0x80000000U / counts_per_usec))
451 counts = (0x80000000U / counts_per_usec) - 1;
453 counts = usec * counts_per_usec;
455 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
458 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
459 counts -= (int32_t)(last - first);
465 * Supply a DELAY() implementation via weak linkage. A platform may want to use
466 * the mpcore per-cpu eventtimers but provide its own DELAY() routine,
467 * especially when the core frequency can change on the fly.
469 __weak_reference(arm_tmr_DELAY, DELAY);