2 * Copyright (c) 2012 Olivier Houchard <cognet@FreeBSD.org>
4 * Ben Gray <ben.r.gray@gmail.com>.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company nor the name of the author may be used to
16 * endorse or promote products derived from this software without specific
17 * prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
24 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
25 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
26 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
27 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
28 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <machine/intr.h>
43 #include <machine/bus.h>
44 #include <machine/pl310.h>
46 #include <machine/platformvar.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
54 #include "platform_pl310_if.h"
58 * Define this if you need to disable PL310 for debugging purpose
60 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/DDI0246E_l2c310_r3p1_trm.pdf
64 * Hardcode errata for now
65 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246b/pr01s02s02.html
67 #define PL310_ERRATA_588369
68 #define PL310_ERRATA_753970
69 #define PL310_ERRATA_727915
71 #define PL310_LOCK(sc) do { \
72 mtx_lock_spin(&(sc)->sc_mtx); \
75 #define PL310_UNLOCK(sc) do { \
76 mtx_unlock_spin(&(sc)->sc_mtx); \
79 static int pl310_enabled = 1;
80 TUNABLE_INT("hw.pl310.enabled", &pl310_enabled);
82 static uint32_t g_l2cache_way_mask;
84 static const uint32_t g_l2cache_line_size = 32;
85 static const uint32_t g_l2cache_align_mask = (32 - 1);
87 static uint32_t g_l2cache_size;
88 static uint32_t g_way_size;
89 static uint32_t g_ways_assoc;
91 static struct pl310_softc *pl310_softc;
93 static struct ofw_compat_data compat_data[] = {
94 {"arm,pl310", true}, /* Non-standard, FreeBSD. */
95 {"arm,pl310-cache", true},
101 platform_pl310_init(struct pl310_softc *sc)
104 PLATFORM_PL310_INIT(platform_obj(), sc);
108 platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val)
111 PLATFORM_PL310_WRITE_CTRL(platform_obj(), sc, val);
115 platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val)
118 PLATFORM_PL310_WRITE_DEBUG(platform_obj(), sc, val);
123 pl310_print_config(struct pl310_softc *sc)
125 uint32_t aux, prefetch;
126 const char *dis = "disabled";
127 const char *ena = "enabled";
129 aux = pl310_read4(sc, PL310_AUX_CTRL);
130 prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL);
132 device_printf(sc->sc_dev, "Early BRESP response: %s\n",
133 (aux & AUX_CTRL_EARLY_BRESP) ? ena : dis);
134 device_printf(sc->sc_dev, "Instruction prefetch: %s\n",
135 (aux & AUX_CTRL_INSTR_PREFETCH) ? ena : dis);
136 device_printf(sc->sc_dev, "Data prefetch: %s\n",
137 (aux & AUX_CTRL_DATA_PREFETCH) ? ena : dis);
138 device_printf(sc->sc_dev, "Non-secure interrupt control: %s\n",
139 (aux & AUX_CTRL_NS_INT_CTRL) ? ena : dis);
140 device_printf(sc->sc_dev, "Non-secure lockdown: %s\n",
141 (aux & AUX_CTRL_NS_LOCKDOWN) ? ena : dis);
142 device_printf(sc->sc_dev, "Share override: %s\n",
143 (aux & AUX_CTRL_SHARE_OVERRIDE) ? ena : dis);
145 device_printf(sc->sc_dev, "Double linefill: %s\n",
146 (prefetch & PREFETCH_CTRL_DL) ? ena : dis);
147 device_printf(sc->sc_dev, "Instruction prefetch: %s\n",
148 (prefetch & PREFETCH_CTRL_INSTR_PREFETCH) ? ena : dis);
149 device_printf(sc->sc_dev, "Data prefetch: %s\n",
150 (prefetch & PREFETCH_CTRL_DATA_PREFETCH) ? ena : dis);
151 device_printf(sc->sc_dev, "Double linefill on WRAP request: %s\n",
152 (prefetch & PREFETCH_CTRL_DL_ON_WRAP) ? ena : dis);
153 device_printf(sc->sc_dev, "Prefetch drop: %s\n",
154 (prefetch & PREFETCH_CTRL_PREFETCH_DROP) ? ena : dis);
155 device_printf(sc->sc_dev, "Incr double Linefill: %s\n",
156 (prefetch & PREFETCH_CTRL_INCR_DL) ? ena : dis);
157 device_printf(sc->sc_dev, "Not same ID on exclusive sequence: %s\n",
158 (prefetch & PREFETCH_CTRL_NOTSAMEID) ? ena : dis);
159 device_printf(sc->sc_dev, "Prefetch offset: %d\n",
160 (prefetch & PREFETCH_CTRL_OFFSET_MASK));
164 pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
165 uint32_t read, uint32_t write, uint32_t setup)
169 KASSERT(which_reg == PL310_TAG_RAM_CTRL ||
170 which_reg == PL310_DATA_RAM_CTRL,
171 ("bad pl310 ram latency register address"));
173 v = pl310_read4(sc, which_reg);
175 KASSERT(setup <= 8, ("bad pl310 setup latency: %d", setup));
176 v &= ~RAM_CTRL_SETUP_MASK;
177 v |= (setup - 1) << RAM_CTRL_SETUP_SHIFT;
180 KASSERT(read <= 8, ("bad pl310 read latency: %d", read));
181 v &= ~RAM_CTRL_READ_MASK;
182 v |= (read - 1) << RAM_CTRL_READ_SHIFT;
185 KASSERT(write <= 8, ("bad pl310 write latency: %d", write));
186 v &= ~RAM_CTRL_WRITE_MASK;
187 v |= (write - 1) << RAM_CTRL_WRITE_SHIFT;
189 pl310_write4(sc, which_reg, v);
193 pl310_filter(void *arg)
195 struct pl310_softc *sc = arg;
198 intr = pl310_read4(sc, PL310_INTR_MASK);
200 if (!sc->sc_enabled && (intr & INTR_MASK_ECNTR)) {
202 * This is for debug purpose, so be blunt about it
203 * We disable PL310 only when something fishy is going
204 * on and we need to make sure L2 cache is 100% disabled
206 panic("pl310: caches disabled but cache event detected\n");
209 return (FILTER_HANDLED);
213 pl310_wait_background_op(uint32_t off, uint32_t mask)
216 while (pl310_read4(pl310_softc, off) & mask)
222 * pl310_cache_sync - performs a cache sync operation
224 * According to the TRM:
226 * "Before writing to any other register you must perform an explicit
227 * Cache Sync operation. This is particularly important when the cache is
228 * enabled and changes to how the cache allocates new lines are to be made."
233 pl310_cache_sync(void)
236 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
239 /* Do not sync outer cache on IO coherent platform */
240 if (pl310_softc->sc_io_coherent)
243 #ifdef PL310_ERRATA_753970
244 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
245 /* Write uncached PL310 register */
246 pl310_write4(pl310_softc, 0x740, 0xffffffff);
249 pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
254 pl310_wbinv_all(void)
257 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
260 PL310_LOCK(pl310_softc);
261 #ifdef PL310_ERRATA_727915
262 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0) {
265 for (i = 0; i < g_ways_assoc; i++) {
266 for (j = 0; j < g_way_size / g_l2cache_line_size; j++) {
267 pl310_write4(pl310_softc,
268 PL310_CLEAN_INV_LINE_IDX,
273 PL310_UNLOCK(pl310_softc);
277 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
278 platform_pl310_write_debug(pl310_softc, 3);
280 pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
281 pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
283 #ifdef PL310_ERRATA_727915
284 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
285 platform_pl310_write_debug(pl310_softc, 0);
287 PL310_UNLOCK(pl310_softc);
291 pl310_wbinv_range(vm_paddr_t start, vm_size_t size)
294 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
297 PL310_LOCK(pl310_softc);
298 if (start & g_l2cache_align_mask) {
299 size += start & g_l2cache_align_mask;
300 start &= ~g_l2cache_align_mask;
302 if (size & g_l2cache_align_mask) {
303 size &= ~g_l2cache_align_mask;
304 size += g_l2cache_line_size;
308 #ifdef PL310_ERRATA_727915
309 if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
310 pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
311 platform_pl310_write_debug(pl310_softc, 3);
314 #ifdef PL310_ERRATA_588369
315 if (pl310_softc->sc_rtl_revision <= CACHE_ID_RELEASE_r1p0) {
317 * Errata 588369 says that clean + inv may keep the
318 * cache line if it was clean, the recommanded
319 * workaround is to clean then invalidate the cache
320 * line, with write-back and cache linefill disabled.
322 pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
323 pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
326 pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA,
328 start += g_l2cache_line_size;
329 size -= g_l2cache_line_size;
331 #ifdef PL310_ERRATA_727915
332 if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
333 pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
334 platform_pl310_write_debug(pl310_softc, 0);
338 PL310_UNLOCK(pl310_softc);
342 pl310_wb_range(vm_paddr_t start, vm_size_t size)
345 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
348 PL310_LOCK(pl310_softc);
349 if (start & g_l2cache_align_mask) {
350 size += start & g_l2cache_align_mask;
351 start &= ~g_l2cache_align_mask;
354 if (size & g_l2cache_align_mask) {
355 size &= ~g_l2cache_align_mask;
356 size += g_l2cache_line_size;
360 pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
361 start += g_l2cache_line_size;
362 size -= g_l2cache_line_size;
366 PL310_UNLOCK(pl310_softc);
370 pl310_inv_range(vm_paddr_t start, vm_size_t size)
373 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
376 PL310_LOCK(pl310_softc);
377 if (start & g_l2cache_align_mask) {
378 size += start & g_l2cache_align_mask;
379 start &= ~g_l2cache_align_mask;
381 if (size & g_l2cache_align_mask) {
382 size &= ~g_l2cache_align_mask;
383 size += g_l2cache_line_size;
386 pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
387 start += g_l2cache_line_size;
388 size -= g_l2cache_line_size;
392 PL310_UNLOCK(pl310_softc);
396 pl310_drain_writebuf(void)
399 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
402 PL310_LOCK(pl310_softc);
404 PL310_UNLOCK(pl310_softc);
408 pl310_set_way_sizes(struct pl310_softc *sc)
412 aux_value = pl310_read4(sc, PL310_AUX_CTRL);
413 g_way_size = (aux_value & AUX_CTRL_WAY_SIZE_MASK) >>
414 AUX_CTRL_WAY_SIZE_SHIFT;
415 g_way_size = 1 << (g_way_size + 13);
416 if (aux_value & (1 << AUX_CTRL_ASSOCIATIVITY_SHIFT))
420 g_l2cache_way_mask = (1 << g_ways_assoc) - 1;
421 g_l2cache_size = g_way_size * g_ways_assoc;
425 * Setup interrupt handling. This is done only if the cache controller is
426 * disabled, for debugging. We set counters so when a cache event happens we'll
427 * get interrupted and be warned that something is wrong, because no cache
428 * events should happen if we're disabled.
431 pl310_config_intr(void *arg)
433 struct pl310_softc * sc;
437 /* activate the interrupt */
438 bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
439 pl310_filter, NULL, sc, &sc->sc_irq_h);
441 /* Cache Line Eviction for Counter 0 */
442 pl310_write4(sc, PL310_EVENT_COUNTER0_CONF,
443 EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_CO);
444 /* Data Read Request for Counter 1 */
445 pl310_write4(sc, PL310_EVENT_COUNTER1_CONF,
446 EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_DRREQ);
448 /* Enable and clear pending interrupts */
449 pl310_write4(sc, PL310_INTR_CLEAR, INTR_MASK_ECNTR);
450 pl310_write4(sc, PL310_INTR_MASK, INTR_MASK_ALL);
452 /* Enable counters and reset C0 and C1 */
453 pl310_write4(sc, PL310_EVENT_COUNTER_CTRL,
454 EVENT_COUNTER_CTRL_ENABLED |
455 EVENT_COUNTER_CTRL_C0_RESET |
456 EVENT_COUNTER_CTRL_C1_RESET);
458 config_intrhook_disestablish(sc->sc_ich);
459 free(sc->sc_ich, M_DEVBUF);
464 pl310_probe(device_t dev)
467 if (!ofw_bus_status_okay(dev))
469 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
471 device_set_desc(dev, "PL310 L2 cache controller");
476 pl310_attach(device_t dev)
478 struct pl310_softc *sc = device_get_softc(dev);
480 uint32_t cache_id, debug_ctrl;
485 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
487 if (sc->sc_mem_res == NULL)
488 panic("%s: Cannot map registers", device_get_name(dev));
490 /* Allocate an IRQ resource */
492 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
493 RF_ACTIVE | RF_SHAREABLE);
494 if (sc->sc_irq_res == NULL) {
495 device_printf(dev, "cannot allocate IRQ, not using interrupt\n");
499 mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN);
501 cache_id = pl310_read4(sc, PL310_CACHE_ID);
502 sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) &
503 CACHE_ID_RELEASE_MASK;
504 device_printf(dev, "Part number: 0x%x, release: 0x%x\n",
505 (cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK,
506 (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK);
509 * Test for "arm,io-coherent" property and disable sync operation if
510 * platform is I/O coherent. Outer sync operations are not needed
511 * on coherent platform and may be harmful in certain situations.
513 node = ofw_bus_get_node(dev);
514 if (OF_hasprop(node, "arm,io-coherent"))
515 sc->sc_io_coherent = true;
518 * If L2 cache is already enabled then something has violated the rules,
519 * because caches are supposed to be off at kernel entry. The cache
520 * must be disabled to write the configuration registers without
521 * triggering an access error (SLVERR), but there's no documented safe
522 * procedure for disabling the L2 cache in the manual. So we'll try to
524 * - Use the debug register to force write-through mode and prevent
525 * linefills (allocation of new lines on read); now anything we do
526 * will not cause new data to come into the L2 cache.
527 * - Writeback and invalidate the current contents.
528 * - Disable the controller.
529 * - Restore the original debug settings.
531 if (pl310_read4(sc, PL310_CTRL) & CTRL_ENABLED) {
532 device_printf(dev, "Warning: L2 Cache should not already be "
533 "active; trying to de-activate and re-initialize...\n");
535 debug_ctrl = pl310_read4(sc, PL310_DEBUG_CTRL);
536 platform_pl310_write_debug(sc, debug_ctrl |
537 DEBUG_CTRL_DISABLE_WRITEBACK | DEBUG_CTRL_DISABLE_LINEFILL);
538 pl310_set_way_sizes(sc);
540 platform_pl310_write_ctrl(sc, CTRL_DISABLED);
541 platform_pl310_write_debug(sc, debug_ctrl);
543 sc->sc_enabled = pl310_enabled;
545 if (sc->sc_enabled) {
546 platform_pl310_init(sc);
547 pl310_set_way_sizes(sc); /* platform init might change these */
548 pl310_write4(pl310_softc, PL310_INV_WAY, 0xffff);
549 pl310_wait_background_op(PL310_INV_WAY, 0xffff);
550 platform_pl310_write_ctrl(sc, CTRL_ENABLED);
551 device_printf(dev, "L2 Cache enabled: %uKB/%dB %d ways\n",
552 (g_l2cache_size / 1024), g_l2cache_line_size, g_ways_assoc);
554 pl310_print_config(sc);
556 if (sc->sc_irq_res != NULL) {
557 sc->sc_ich = malloc(sizeof(*sc->sc_ich), M_DEVBUF, M_WAITOK);
558 sc->sc_ich->ich_func = pl310_config_intr;
559 sc->sc_ich->ich_arg = sc;
560 if (config_intrhook_establish(sc->sc_ich) != 0) {
562 "config_intrhook_establish failed\n");
563 free(sc->sc_ich, M_DEVBUF);
568 device_printf(dev, "L2 Cache disabled\n");
571 /* Set the l2 functions in the set of cpufuncs */
572 cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all;
573 cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range;
574 cpufuncs.cf_l2cache_inv_range = pl310_inv_range;
575 cpufuncs.cf_l2cache_wb_range = pl310_wb_range;
576 cpufuncs.cf_l2cache_drain_writebuf = pl310_drain_writebuf;
581 static device_method_t pl310_methods[] = {
582 DEVMETHOD(device_probe, pl310_probe),
583 DEVMETHOD(device_attach, pl310_attach),
587 static driver_t pl310_driver = {
590 sizeof(struct pl310_softc),
592 static devclass_t pl310_devclass;
594 EARLY_DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0,
595 BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE);