sys/arm/arm/pl310.c

   1 /*-
   2  * Copyright (c) 2012 Olivier Houchard <cognet@FreeBSD.org>
   3  * Copyright (c) 2011
   4  *      Ben Gray <ben.r.gray@gmail.com>.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the company nor the name of the author may be used to
  16  *    endorse or promote products derived from this software without specific
  17  *    prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  24  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  25  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  26  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  27  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  28  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/kernel.h>
  37 #include <sys/rman.h>
  38 #include <sys/module.h>
  39 #include <sys/lock.h>
  40 #include <sys/mutex.h>
  41 #include <machine/intr.h>
  42
  43 #include <machine/bus.h>
  44 #include <machine/pl310.h>
  45 #ifdef PLATFORM
  46 #include <machine/platformvar.h>
  47 #endif
  48
  49 #include <dev/ofw/openfirm.h>
  50 #include <dev/ofw/ofw_bus.h>
  51 #include <dev/ofw/ofw_bus_subr.h>
  52
  53 #ifdef PLATFORM
  54 #include "platform_pl310_if.h"
  55 #endif
  56
  57 /*
  58  * Define this if you need to disable PL310 for debugging purpose
  59  * Spec:
  60  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/DDI0246E_l2c310_r3p1_trm.pdf
  61  */
  62
  63 /*
  64  * Hardcode errata for now
  65  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246b/pr01s02s02.html
  66  */
  67 #define PL310_ERRATA_588369
  68 #define PL310_ERRATA_753970
  69 #define PL310_ERRATA_727915
  70
  71 #define PL310_LOCK(sc) do {             \
  72         mtx_lock_spin(&(sc)->sc_mtx);   \
  73 } while(0);
  74
  75 #define PL310_UNLOCK(sc) do {           \
  76         mtx_unlock_spin(&(sc)->sc_mtx); \
  77 } while(0);
  78
  79 static int pl310_enabled = 1;
  80 TUNABLE_INT("hw.pl310.enabled", &pl310_enabled);
  81
  82 static uint32_t g_l2cache_way_mask;
  83
  84 static const uint32_t g_l2cache_line_size = 32;
  85 static const uint32_t g_l2cache_align_mask = (32 - 1);
  86
  87 static uint32_t g_l2cache_size;
  88 static uint32_t g_way_size;
  89 static uint32_t g_ways_assoc;
  90
  91 static struct pl310_softc *pl310_softc;
  92
  93 static struct ofw_compat_data compat_data[] = {
  94         {"arm,pl310",           true}, /* Non-standard, FreeBSD. */
  95         {"arm,pl310-cache",     true},
  96         {NULL,                  false}
  97 };
  98
  99 #ifdef PLATFORM
 100 static void
 101 platform_pl310_init(struct pl310_softc *sc)
 102 {
 103
 104         PLATFORM_PL310_INIT(platform_obj(), sc);
 105 }
 106
 107 static void
 108 platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val)
 109 {
 110
 111         PLATFORM_PL310_WRITE_CTRL(platform_obj(), sc, val);
 112 }
 113
 114 static void
 115 platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val)
 116 {
 117
 118         PLATFORM_PL310_WRITE_DEBUG(platform_obj(), sc, val);
 119 }
 120 #endif
 121
 122 static void
 123 pl310_print_config(struct pl310_softc *sc)
 124 {
 125         uint32_t aux, prefetch;
 126         const char *dis = "disabled";
 127         const char *ena = "enabled";
 128
 129         aux = pl310_read4(sc, PL310_AUX_CTRL);
 130         prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL);
 131
 132         device_printf(sc->sc_dev, "Early BRESP response: %s\n",
 133                 (aux & AUX_CTRL_EARLY_BRESP) ? ena : dis);
 134         device_printf(sc->sc_dev, "Instruction prefetch: %s\n",
 135                 (aux & AUX_CTRL_INSTR_PREFETCH) ? ena : dis);
 136         device_printf(sc->sc_dev, "Data prefetch: %s\n",
 137                 (aux & AUX_CTRL_DATA_PREFETCH) ? ena : dis);
 138         device_printf(sc->sc_dev, "Non-secure interrupt control: %s\n",
 139                 (aux & AUX_CTRL_NS_INT_CTRL) ? ena : dis);
 140         device_printf(sc->sc_dev, "Non-secure lockdown: %s\n",
 141                 (aux & AUX_CTRL_NS_LOCKDOWN) ? ena : dis);
 142         device_printf(sc->sc_dev, "Share override: %s\n",
 143                 (aux & AUX_CTRL_SHARE_OVERRIDE) ? ena : dis);
 144
 145         device_printf(sc->sc_dev, "Double linefill: %s\n",
 146                 (prefetch & PREFETCH_CTRL_DL) ? ena : dis);
 147         device_printf(sc->sc_dev, "Instruction prefetch: %s\n",
 148                 (prefetch & PREFETCH_CTRL_INSTR_PREFETCH) ? ena : dis);
 149         device_printf(sc->sc_dev, "Data prefetch: %s\n",
 150                 (prefetch & PREFETCH_CTRL_DATA_PREFETCH) ? ena : dis);
 151         device_printf(sc->sc_dev, "Double linefill on WRAP request: %s\n",
 152                 (prefetch & PREFETCH_CTRL_DL_ON_WRAP) ? ena : dis);
 153         device_printf(sc->sc_dev, "Prefetch drop: %s\n",
 154                 (prefetch & PREFETCH_CTRL_PREFETCH_DROP) ? ena : dis);
 155         device_printf(sc->sc_dev, "Incr double Linefill: %s\n",
 156                 (prefetch & PREFETCH_CTRL_INCR_DL) ? ena : dis);
 157         device_printf(sc->sc_dev, "Not same ID on exclusive sequence: %s\n",
 158                 (prefetch & PREFETCH_CTRL_NOTSAMEID) ? ena : dis);
 159         device_printf(sc->sc_dev, "Prefetch offset: %d\n",
 160                 (prefetch & PREFETCH_CTRL_OFFSET_MASK));
 161 }
 162
 163 void
 164 pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
 165    uint32_t read, uint32_t write, uint32_t setup)
 166 {
 167         uint32_t v;
 168
 169         KASSERT(which_reg == PL310_TAG_RAM_CTRL ||
 170             which_reg == PL310_DATA_RAM_CTRL,
 171             ("bad pl310 ram latency register address"));
 172
 173         v = pl310_read4(sc, which_reg);
 174         if (setup != 0) {
 175                 KASSERT(setup <= 8, ("bad pl310 setup latency: %d", setup));
 176                 v &= ~RAM_CTRL_SETUP_MASK;
 177                 v |= (setup - 1) << RAM_CTRL_SETUP_SHIFT;
 178         }
 179         if (read != 0) {
 180                 KASSERT(read <= 8, ("bad pl310 read latency: %d", read));
 181                 v &= ~RAM_CTRL_READ_MASK;
 182                 v |= (read - 1) << RAM_CTRL_READ_SHIFT;
 183         }
 184         if (write != 0) {
 185                 KASSERT(write <= 8, ("bad pl310 write latency: %d", write));
 186                 v &= ~RAM_CTRL_WRITE_MASK;
 187                 v |= (write - 1) << RAM_CTRL_WRITE_SHIFT;
 188         }
 189         pl310_write4(sc, which_reg, v);
 190 }
 191
 192 static int
 193 pl310_filter(void *arg)
 194 {
 195         struct pl310_softc *sc = arg;
 196         uint32_t intr;
 197
 198         intr = pl310_read4(sc, PL310_INTR_MASK);
 199
 200         if (!sc->sc_enabled && (intr & INTR_MASK_ECNTR)) {
 201                 /*
 202                  * This is for debug purpose, so be blunt about it
 203                  * We disable PL310 only when something fishy is going
 204                  * on and we need to make sure L2 cache is 100% disabled
 205                  */
 206                 panic("pl310: caches disabled but cache event detected\n");
 207         }
 208
 209         return (FILTER_HANDLED);
 210 }
 211
 212 static __inline void
 213 pl310_wait_background_op(uint32_t off, uint32_t mask)
 214 {
 215
 216         while (pl310_read4(pl310_softc, off) & mask)
 217                 continue;
 218 }
 219
 220
 221 /**
 222  *      pl310_cache_sync - performs a cache sync operation
 223  *
 224  *      According to the TRM:
 225  *
 226  *  "Before writing to any other register you must perform an explicit
 227  *   Cache Sync operation. This is particularly important when the cache is
 228  *   enabled and changes to how the cache allocates new lines are to be made."
 229  *
 230  *
 231  */
 232 static __inline void
 233 pl310_cache_sync(void)
 234 {
 235
 236         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 237                 return;
 238
 239         /* Do not sync outer cache on IO coherent platform */
 240         if (pl310_softc->sc_io_coherent)
 241                 return;
 242
 243 #ifdef PL310_ERRATA_753970
 244         if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
 245                 /* Write uncached PL310 register */
 246                 pl310_write4(pl310_softc, 0x740, 0xffffffff);
 247         else
 248 #endif
 249                 pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
 250 }
 251
 252
 253 static void
 254 pl310_wbinv_all(void)
 255 {
 256
 257         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 258                 return;
 259
 260         PL310_LOCK(pl310_softc);
 261 #ifdef PL310_ERRATA_727915
 262         if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0) {
 263                 int i, j;
 264
 265                 for (i = 0; i < g_ways_assoc; i++) {
 266                         for (j = 0; j < g_way_size / g_l2cache_line_size; j++) {
 267                                 pl310_write4(pl310_softc,
 268                                     PL310_CLEAN_INV_LINE_IDX,
 269                                     (i << 28 | j << 5));
 270                         }
 271                 }
 272                 pl310_cache_sync();
 273                 PL310_UNLOCK(pl310_softc);
 274                 return;
 275
 276         }
 277         if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
 278                 platform_pl310_write_debug(pl310_softc, 3);
 279 #endif
 280         pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
 281         pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
 282         pl310_cache_sync();
 283 #ifdef PL310_ERRATA_727915
 284         if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
 285                 platform_pl310_write_debug(pl310_softc, 0);
 286 #endif
 287         PL310_UNLOCK(pl310_softc);
 288 }
 289
 290 static void
 291 pl310_wbinv_range(vm_paddr_t start, vm_size_t size)
 292 {
 293
 294         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 295                 return;
 296
 297         PL310_LOCK(pl310_softc);
 298         if (start & g_l2cache_align_mask) {
 299                 size += start & g_l2cache_align_mask;
 300                 start &= ~g_l2cache_align_mask;
 301         }
 302         if (size & g_l2cache_align_mask) {
 303                 size &= ~g_l2cache_align_mask;
 304                 size += g_l2cache_line_size;
 305         }
 306
 307
 308 #ifdef PL310_ERRATA_727915
 309         if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
 310             pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
 311                 platform_pl310_write_debug(pl310_softc, 3);
 312 #endif
 313         while (size > 0) {
 314 #ifdef PL310_ERRATA_588369
 315                 if (pl310_softc->sc_rtl_revision <= CACHE_ID_RELEASE_r1p0) {
 316                         /*
 317                          * Errata 588369 says that clean + inv may keep the
 318                          * cache line if it was clean, the recommanded
 319                          * workaround is to clean then invalidate the cache
 320                          * line, with write-back and cache linefill disabled.
 321                          */
 322                         pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
 323                         pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
 324                 } else
 325 #endif
 326                         pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA,
 327                             start);
 328                 start += g_l2cache_line_size;
 329                 size -= g_l2cache_line_size;
 330         }
 331 #ifdef PL310_ERRATA_727915
 332         if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
 333             pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
 334                 platform_pl310_write_debug(pl310_softc, 0);
 335 #endif
 336
 337         pl310_cache_sync();
 338         PL310_UNLOCK(pl310_softc);
 339 }
 340
 341 static void
 342 pl310_wb_range(vm_paddr_t start, vm_size_t size)
 343 {
 344
 345         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 346                 return;
 347
 348         PL310_LOCK(pl310_softc);
 349         if (start & g_l2cache_align_mask) {
 350                 size += start & g_l2cache_align_mask;
 351                 start &= ~g_l2cache_align_mask;
 352         }
 353
 354         if (size & g_l2cache_align_mask) {
 355                 size &= ~g_l2cache_align_mask;
 356                 size += g_l2cache_line_size;
 357         }
 358
 359         while (size > 0) {
 360                 pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
 361                 start += g_l2cache_line_size;
 362                 size -= g_l2cache_line_size;
 363         }
 364
 365         pl310_cache_sync();
 366         PL310_UNLOCK(pl310_softc);
 367 }
 368
 369 static void
 370 pl310_inv_range(vm_paddr_t start, vm_size_t size)
 371 {
 372
 373         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 374                 return;
 375
 376         PL310_LOCK(pl310_softc);
 377         if (start & g_l2cache_align_mask) {
 378                 size += start & g_l2cache_align_mask;
 379                 start &= ~g_l2cache_align_mask;
 380         }
 381         if (size & g_l2cache_align_mask) {
 382                 size &= ~g_l2cache_align_mask;
 383                 size += g_l2cache_line_size;
 384         }
 385         while (size > 0) {
 386                 pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
 387                 start += g_l2cache_line_size;
 388                 size -= g_l2cache_line_size;
 389         }
 390
 391         pl310_cache_sync();
 392         PL310_UNLOCK(pl310_softc);
 393 }
 394
 395 static void
 396 pl310_drain_writebuf(void)
 397 {
 398
 399         if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
 400                 return;
 401
 402         PL310_LOCK(pl310_softc);
 403         pl310_cache_sync();
 404         PL310_UNLOCK(pl310_softc);
 405 }
 406
 407 static void
 408 pl310_set_way_sizes(struct pl310_softc *sc)
 409 {
 410         uint32_t aux_value;
 411
 412         aux_value = pl310_read4(sc, PL310_AUX_CTRL);
 413         g_way_size = (aux_value & AUX_CTRL_WAY_SIZE_MASK) >>
 414             AUX_CTRL_WAY_SIZE_SHIFT;
 415         g_way_size = 1 << (g_way_size + 13);
 416         if (aux_value & (1 << AUX_CTRL_ASSOCIATIVITY_SHIFT))
 417                 g_ways_assoc = 16;
 418         else
 419                 g_ways_assoc = 8;
 420         g_l2cache_way_mask = (1 << g_ways_assoc) - 1;
 421         g_l2cache_size = g_way_size * g_ways_assoc;
 422 }
 423
 424 /*
 425  * Setup interrupt handling.  This is done only if the cache controller is
 426  * disabled, for debugging.  We set counters so when a cache event happens we'll
 427  * get interrupted and be warned that something is wrong, because no cache
 428  * events should happen if we're disabled.
 429  */
 430 static void
 431 pl310_config_intr(void *arg)
 432 {
 433         struct pl310_softc * sc;
 434
 435         sc = arg;
 436
 437         /* activate the interrupt */
 438         bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 439             pl310_filter, NULL, sc, &sc->sc_irq_h);
 440
 441         /* Cache Line Eviction for Counter 0 */
 442         pl310_write4(sc, PL310_EVENT_COUNTER0_CONF,
 443             EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_CO);
 444         /* Data Read Request for Counter 1 */
 445         pl310_write4(sc, PL310_EVENT_COUNTER1_CONF,
 446             EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_DRREQ);
 447
 448         /* Enable and clear pending interrupts */
 449         pl310_write4(sc, PL310_INTR_CLEAR, INTR_MASK_ECNTR);
 450         pl310_write4(sc, PL310_INTR_MASK, INTR_MASK_ALL);
 451
 452         /* Enable counters and reset C0 and C1 */
 453         pl310_write4(sc, PL310_EVENT_COUNTER_CTRL,
 454             EVENT_COUNTER_CTRL_ENABLED |
 455             EVENT_COUNTER_CTRL_C0_RESET |
 456             EVENT_COUNTER_CTRL_C1_RESET);
 457
 458         config_intrhook_disestablish(sc->sc_ich);
 459         free(sc->sc_ich, M_DEVBUF);
 460         sc->sc_ich = NULL;
 461 }
 462
 463 static int
 464 pl310_probe(device_t dev)
 465 {
 466
 467         if (!ofw_bus_status_okay(dev))
 468                 return (ENXIO);
 469         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 470                 return (ENXIO);
 471         device_set_desc(dev, "PL310 L2 cache controller");
 472         return (0);
 473 }
 474
 475 static int
 476 pl310_attach(device_t dev)
 477 {
 478         struct pl310_softc *sc = device_get_softc(dev);
 479         int rid;
 480         uint32_t cache_id, debug_ctrl;
 481         phandle_t node;
 482
 483         sc->sc_dev = dev;
 484         rid = 0;
 485         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 486             RF_ACTIVE);
 487         if (sc->sc_mem_res == NULL)
 488                 panic("%s: Cannot map registers", device_get_name(dev));
 489
 490         /* Allocate an IRQ resource */
 491         rid = 0;
 492         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 493                                                 RF_ACTIVE | RF_SHAREABLE);
 494         if (sc->sc_irq_res == NULL) {
 495                 device_printf(dev, "cannot allocate IRQ, not using interrupt\n");
 496         }
 497
 498         pl310_softc = sc;
 499         mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN);
 500
 501         cache_id = pl310_read4(sc, PL310_CACHE_ID);
 502         sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) &
 503             CACHE_ID_RELEASE_MASK;
 504         device_printf(dev, "Part number: 0x%x, release: 0x%x\n",
 505             (cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK,
 506             (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK);
 507
 508         /*
 509          * Test for "arm,io-coherent" property and disable sync operation if
 510          * platform is I/O coherent. Outer sync operations are not needed
 511          * on coherent platform and may be harmful in certain situations.
 512          */
 513         node = ofw_bus_get_node(dev);
 514         if (OF_hasprop(node, "arm,io-coherent"))
 515                 sc->sc_io_coherent = true;
 516
 517         /*
 518          * If L2 cache is already enabled then something has violated the rules,
 519          * because caches are supposed to be off at kernel entry.  The cache
 520          * must be disabled to write the configuration registers without
 521          * triggering an access error (SLVERR), but there's no documented safe
 522          * procedure for disabling the L2 cache in the manual.  So we'll try to
 523          * invent one:
 524          *  - Use the debug register to force write-through mode and prevent
 525          *    linefills (allocation of new lines on read); now anything we do
 526          *    will not cause new data to come into the L2 cache.
 527          *  - Writeback and invalidate the current contents.
 528          *  - Disable the controller.
 529          *  - Restore the original debug settings.
 530          */
 531         if (pl310_read4(sc, PL310_CTRL) & CTRL_ENABLED) {
 532                 device_printf(dev, "Warning: L2 Cache should not already be "
 533                     "active; trying to de-activate and re-initialize...\n");
 534                 sc->sc_enabled = 1;
 535                 debug_ctrl = pl310_read4(sc, PL310_DEBUG_CTRL);
 536                 platform_pl310_write_debug(sc, debug_ctrl |
 537                     DEBUG_CTRL_DISABLE_WRITEBACK | DEBUG_CTRL_DISABLE_LINEFILL);
 538                 pl310_set_way_sizes(sc);
 539                 pl310_wbinv_all();
 540                 platform_pl310_write_ctrl(sc, CTRL_DISABLED);
 541                 platform_pl310_write_debug(sc, debug_ctrl);
 542         }
 543         sc->sc_enabled = pl310_enabled;
 544
 545         if (sc->sc_enabled) {
 546                 platform_pl310_init(sc);
 547                 pl310_set_way_sizes(sc); /* platform init might change these */
 548                 pl310_write4(pl310_softc, PL310_INV_WAY, 0xffff);
 549                 pl310_wait_background_op(PL310_INV_WAY, 0xffff);
 550                 platform_pl310_write_ctrl(sc, CTRL_ENABLED);
 551                 device_printf(dev, "L2 Cache enabled: %uKB/%dB %d ways\n",
 552                     (g_l2cache_size / 1024), g_l2cache_line_size, g_ways_assoc);
 553                 if (bootverbose)
 554                         pl310_print_config(sc);
 555         } else {
 556                 if (sc->sc_irq_res != NULL) {
 557                         sc->sc_ich = malloc(sizeof(*sc->sc_ich), M_DEVBUF, M_WAITOK);
 558                         sc->sc_ich->ich_func = pl310_config_intr;
 559                         sc->sc_ich->ich_arg = sc;
 560                         if (config_intrhook_establish(sc->sc_ich) != 0) {
 561                                 device_printf(dev,
 562                                     "config_intrhook_establish failed\n");
 563                                 free(sc->sc_ich, M_DEVBUF);
 564                                 return(ENXIO);
 565                         }
 566                 }
 567
 568                 device_printf(dev, "L2 Cache disabled\n");
 569         }
 570
 571         /* Set the l2 functions in the set of cpufuncs */
 572         cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all;
 573         cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range;
 574         cpufuncs.cf_l2cache_inv_range = pl310_inv_range;
 575         cpufuncs.cf_l2cache_wb_range = pl310_wb_range;
 576         cpufuncs.cf_l2cache_drain_writebuf = pl310_drain_writebuf;
 577
 578         return (0);
 579 }
 580
 581 static device_method_t pl310_methods[] = {
 582         DEVMETHOD(device_probe, pl310_probe),
 583         DEVMETHOD(device_attach, pl310_attach),
 584         DEVMETHOD_END
 585 };
 586
 587 static driver_t pl310_driver = {
 588         "l2cache",
 589         pl310_methods,
 590         sizeof(struct pl310_softc),
 591 };
 592 static devclass_t pl310_devclass;
 593
 594 EARLY_DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0,
 595     BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE);
 596