1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependent vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
140 /* Include header files */
144 #include <sys/cdefs.h>
145 __FBSDID("$FreeBSD$");
146 #include <sys/param.h>
147 #include <sys/systm.h>
148 #include <sys/kernel.h>
150 #include <sys/lock.h>
151 #include <sys/proc.h>
152 #include <sys/malloc.h>
153 #include <sys/msgbuf.h>
154 #include <sys/mutex.h>
155 #include <sys/vmmeter.h>
156 #include <sys/mman.h>
157 #include <sys/rwlock.h>
159 #include <sys/sched.h>
162 #include <vm/vm_param.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_phys.h>
171 #include <vm/vm_pagequeue.h>
172 #include <vm/vm_extern.h>
174 #include <machine/md_var.h>
175 #include <machine/cpu.h>
176 #include <machine/cpufunc.h>
177 #include <machine/pcb.h>
180 #define PDEBUG(_lev_,_stat_) \
181 if (pmap_debug_level >= (_lev_)) \
183 #define dprintf printf
185 int pmap_debug_level = 0;
187 #else /* PMAP_DEBUG */
188 #define PDEBUG(_lev_,_stat_) /* Nothing */
189 #define dprintf(x, arg...)
190 #define PMAP_INLINE __inline
191 #endif /* PMAP_DEBUG */
193 extern struct pv_addr systempage;
195 extern int last_fault_code;
197 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
198 #define l2pte_index(v) (((v) & L1_S_OFFSET) >> L2_S_SHIFT)
199 #define l2pte_valid(pte) ((pte) != 0)
200 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
203 * Internal function prototypes
205 static void pmap_free_pv_entry (pv_entry_t);
206 static pv_entry_t pmap_get_pv_entry(void);
208 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
210 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
211 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
212 static void pmap_alloc_l1(pmap_t);
213 static void pmap_free_l1(pmap_t);
215 static int pmap_clearbit(struct vm_page *, u_int);
217 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
218 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
219 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
220 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
222 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
224 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
225 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
226 vm_offset_t pmap_curmaxkvaddr;
227 vm_paddr_t kernel_l1pa;
229 vm_offset_t kernel_vm_end = 0;
231 vm_offset_t vm_max_kernel_address;
233 struct pmap kernel_pmap_store;
235 static pt_entry_t *csrc_pte, *cdst_pte;
236 static vm_offset_t csrcp, cdstp, qmap_addr;
237 static struct mtx cmtx, qmap_mtx;
239 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
241 * These routines are called when the CPU type is identified to set up
242 * the PTE prototypes, cache modes, etc.
244 * The variables are always here, just in case LKMs need to reference
245 * them (though, they shouldn't).
248 static pt_entry_t pte_l1_s_cache_mode;
249 static pt_entry_t pte_l1_s_cache_mode_pt;
250 static pt_entry_t pte_l1_s_cache_mask;
252 static pt_entry_t pte_l2_l_cache_mode;
253 static pt_entry_t pte_l2_l_cache_mode_pt;
254 static pt_entry_t pte_l2_l_cache_mask;
256 static pt_entry_t pte_l2_s_cache_mode;
257 static pt_entry_t pte_l2_s_cache_mode_pt;
258 static pt_entry_t pte_l2_s_cache_mask;
263 static caddr_t crashdumpmap;
265 extern void bcopy_page(vm_offset_t, vm_offset_t);
266 extern void bzero_page(vm_offset_t);
268 extern vm_offset_t alloc_firstaddr;
273 * Metadata for L1 translation tables.
276 /* Entry on the L1 Table list */
277 SLIST_ENTRY(l1_ttable) l1_link;
279 /* Entry on the L1 Least Recently Used list */
280 TAILQ_ENTRY(l1_ttable) l1_lru;
282 /* Track how many domains are allocated from this L1 */
283 volatile u_int l1_domain_use_count;
286 * A free-list of domain numbers for this L1.
287 * We avoid using ffs() and a bitmap to track domains since ffs()
290 u_int8_t l1_domain_first;
291 u_int8_t l1_domain_free[PMAP_DOMAINS];
293 /* Physical address of this L1 page table */
294 vm_paddr_t l1_physaddr;
296 /* KVA of this L1 page table */
301 * Convert a virtual address into its L1 table index. That is, the
302 * index used to locate the L2 descriptor table pointer in an L1 table.
303 * This is basically used to index l1->l1_kva[].
305 * Each L2 descriptor table represents 1MB of VA space.
307 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
310 * L1 Page Tables are tracked using a Least Recently Used list.
311 * - New L1s are allocated from the HEAD.
312 * - Freed L1s are added to the TAIl.
313 * - Recently accessed L1s (where an 'access' is some change to one of
314 * the userland pmaps which owns this L1) are moved to the TAIL.
316 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
318 * A list of all L1 tables
320 static SLIST_HEAD(, l1_ttable) l1_list;
321 static struct mtx l1_lru_lock;
324 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
326 * This is normally 16MB worth L2 page descriptors for any given pmap.
327 * Reference counts are maintained for L2 descriptors so they can be
331 /* The number of L2 page descriptors allocated to this l2_dtable */
334 /* List of L2 page descriptors */
336 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
337 vm_paddr_t l2b_phys; /* Physical address of same */
338 u_short l2b_l1idx; /* This L2 table's L1 index */
339 u_short l2b_occupancy; /* How many active descriptors */
340 } l2_bucket[L2_BUCKET_SIZE];
343 /* pmap_kenter_internal flags */
344 #define KENTER_CACHE 0x1
345 #define KENTER_USER 0x2
348 * Given an L1 table index, calculate the corresponding l2_dtable index
349 * and bucket index within the l2_dtable.
351 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
353 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
356 * Given a virtual address, this macro returns the
357 * virtual address required to drop into the next L2 bucket.
359 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
362 * We try to map the page tables write-through, if possible. However, not
363 * all CPUs have a write-through cache mode, so on those we have to sync
364 * the cache when we frob page tables.
366 * We try to evaluate this at compile time, if possible. However, it's
367 * not always possible to do that, hence this run-time var.
369 int pmap_needs_pte_sync;
372 * Macro to determine if a mapping might be resident in the
373 * instruction cache and/or TLB
375 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
378 * Macro to determine if a mapping might be resident in the
379 * data cache and/or TLB
381 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
383 #ifndef PMAP_SHPGPERPROC
384 #define PMAP_SHPGPERPROC 200
387 #define pmap_is_current(pm) ((pm) == kernel_pmap || \
388 curproc->p_vmspace->vm_map.pmap == (pm))
389 static uma_zone_t pvzone = NULL;
391 static uma_zone_t l2table_zone;
392 static vm_offset_t pmap_kernel_l2dtable_kva;
393 static vm_offset_t pmap_kernel_l2ptp_kva;
394 static vm_paddr_t pmap_kernel_l2ptp_phys;
395 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
396 static struct rwlock pvh_global_lock;
398 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
399 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
402 * This list exists for the benefit of pmap_map_chunk(). It keeps track
403 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
404 * find them as necessary.
406 * Note that the data on this list MUST remain valid after initarm() returns,
407 * as pmap_bootstrap() uses it to contruct L2 table metadata.
409 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
412 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
417 l1->l1_domain_use_count = 0;
418 l1->l1_domain_first = 0;
420 for (i = 0; i < PMAP_DOMAINS; i++)
421 l1->l1_domain_free[i] = i + 1;
424 * Copy the kernel's L1 entries to each new L1.
426 if (l1pt != kernel_pmap->pm_l1->l1_kva)
427 memcpy(l1pt, kernel_pmap->pm_l1->l1_kva, L1_TABLE_SIZE);
429 if ((l1->l1_physaddr = pmap_extract(kernel_pmap, (vm_offset_t)l1pt)) == 0)
430 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
431 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
432 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
436 kernel_pt_lookup(vm_paddr_t pa)
440 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
448 pmap_pte_init_generic(void)
451 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
452 pte_l1_s_cache_mask = L1_S_CACHE_MASK;
454 pte_l2_l_cache_mode = L2_B|L2_C;
455 pte_l2_l_cache_mask = L2_L_CACHE_MASK;
457 pte_l2_s_cache_mode = L2_B|L2_C;
458 pte_l2_s_cache_mask = L2_S_CACHE_MASK;
461 * If we have a write-through cache, set B and C. If
462 * we have a write-back cache, then we assume setting
463 * only C will make those pages write-through.
465 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
466 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
467 pte_l2_l_cache_mode_pt = L2_B|L2_C;
468 pte_l2_s_cache_mode_pt = L2_B|L2_C;
470 pte_l1_s_cache_mode_pt = L1_S_C;
471 pte_l2_l_cache_mode_pt = L2_C;
472 pte_l2_s_cache_mode_pt = L2_C;
477 * Allocate an L1 translation table for the specified pmap.
478 * This is called at pmap creation time.
481 pmap_alloc_l1(pmap_t pm)
483 struct l1_ttable *l1;
487 * Remove the L1 at the head of the LRU list
489 mtx_lock(&l1_lru_lock);
490 l1 = TAILQ_FIRST(&l1_lru_list);
491 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
494 * Pick the first available domain number, and update
495 * the link to the next number.
497 domain = l1->l1_domain_first;
498 l1->l1_domain_first = l1->l1_domain_free[domain];
501 * If there are still free domain numbers in this L1,
502 * put it back on the TAIL of the LRU list.
504 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
505 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
507 mtx_unlock(&l1_lru_lock);
510 * Fix up the relevant bits in the pmap structure
513 pm->pm_domain = domain + 1;
517 * Free an L1 translation table.
518 * This is called at pmap destruction time.
521 pmap_free_l1(pmap_t pm)
523 struct l1_ttable *l1 = pm->pm_l1;
525 mtx_lock(&l1_lru_lock);
528 * If this L1 is currently on the LRU list, remove it.
530 if (l1->l1_domain_use_count < PMAP_DOMAINS)
531 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
534 * Free up the domain number which was allocated to the pmap
536 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
537 l1->l1_domain_first = pm->pm_domain - 1;
538 l1->l1_domain_use_count--;
541 * The L1 now must have at least 1 free domain, so add
542 * it back to the LRU list. If the use count is zero,
543 * put it at the head of the list, otherwise it goes
546 if (l1->l1_domain_use_count == 0) {
547 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
549 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
551 mtx_unlock(&l1_lru_lock);
555 * Returns a pointer to the L2 bucket associated with the specified pmap
556 * and VA, or NULL if no L2 bucket exists for the address.
558 static PMAP_INLINE struct l2_bucket *
559 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
561 struct l2_dtable *l2;
562 struct l2_bucket *l2b;
567 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
568 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
575 * Returns a pointer to the L2 bucket associated with the specified pmap
578 * If no L2 bucket exists, perform the necessary allocations to put an L2
579 * bucket/page table in place.
581 * Note that if a new L2 bucket/page was allocated, the caller *must*
582 * increment the bucket occupancy counter appropriately *before*
583 * releasing the pmap's lock to ensure no other thread or cpu deallocates
584 * the bucket/page in the meantime.
586 static struct l2_bucket *
587 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
589 struct l2_dtable *l2;
590 struct l2_bucket *l2b;
595 PMAP_ASSERT_LOCKED(pm);
596 rw_assert(&pvh_global_lock, RA_WLOCKED);
597 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
599 * No mapping at this address, as there is
600 * no entry in the L1 table.
601 * Need to allocate a new l2_dtable.
604 rw_wunlock(&pvh_global_lock);
605 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
606 rw_wlock(&pvh_global_lock);
610 rw_wlock(&pvh_global_lock);
612 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
614 * Someone already allocated the l2_dtable while
615 * we were doing the same.
617 uma_zfree(l2table_zone, l2);
618 l2 = pm->pm_l2[L2_IDX(l1idx)];
620 bzero(l2, sizeof(*l2));
622 * Link it into the parent pmap
624 pm->pm_l2[L2_IDX(l1idx)] = l2;
628 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
631 * Fetch pointer to the L2 page table associated with the address.
633 if (l2b->l2b_kva == NULL) {
637 * No L2 page table has been allocated. Chances are, this
638 * is because we just allocated the l2_dtable, above.
642 rw_wunlock(&pvh_global_lock);
643 ptep = uma_zalloc(l2zone, M_NOWAIT);
644 rw_wlock(&pvh_global_lock);
646 if (l2b->l2b_kva != NULL) {
647 /* We lost the race. */
649 uma_zfree(l2zone, ptep);
652 l2b->l2b_phys = vtophys(ptep);
655 * Oops, no more L2 page tables available at this
656 * time. We may need to deallocate the l2_dtable
657 * if we allocated a new one above.
660 if (l2->l2_occupancy == 0) {
661 pm->pm_l2[L2_IDX(l1idx)] = NULL;
662 uma_zfree(l2table_zone, l2);
668 l2b->l2b_l1idx = l1idx;
674 static PMAP_INLINE void
675 #ifndef PMAP_INCLUDE_PTE_SYNC
676 pmap_free_l2_ptp(pt_entry_t *l2)
678 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
681 #ifdef PMAP_INCLUDE_PTE_SYNC
683 * Note: With a write-back cache, we may need to sync this
684 * L2 table before re-using it.
685 * This is because it may have belonged to a non-current
686 * pmap, in which case the cache syncs would have been
687 * skipped when the pages were being unmapped. If the
688 * L2 table were then to be immediately re-allocated to
689 * the *current* pmap, it may well contain stale mappings
690 * which have not yet been cleared by a cache write-back
691 * and so would still be visible to the mmu.
694 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
696 uma_zfree(l2zone, l2);
699 * One or more mappings in the specified L2 descriptor table have just been
702 * Garbage collect the metadata and descriptor table itself if necessary.
704 * The pmap lock must be acquired when this is called (not necessary
705 * for the kernel pmap).
708 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
710 struct l2_dtable *l2;
711 pd_entry_t *pl1pd, l1pd;
717 * Update the bucket's reference count according to how many
718 * PTEs the caller has just invalidated.
720 l2b->l2b_occupancy -= count;
725 * Level 2 page tables allocated to the kernel pmap are never freed
726 * as that would require checking all Level 1 page tables and
727 * removing any references to the Level 2 page table. See also the
728 * comment elsewhere about never freeing bootstrap L2 descriptors.
730 * We make do with just invalidating the mapping in the L2 table.
732 * This isn't really a big deal in practice and, in fact, leads
733 * to a performance win over time as we don't need to continually
736 if (l2b->l2b_occupancy > 0 || pm == kernel_pmap)
740 * There are no more valid mappings in this level 2 page table.
741 * Go ahead and NULL-out the pointer in the bucket, then
742 * free the page table.
744 l1idx = l2b->l2b_l1idx;
748 pl1pd = &pm->pm_l1->l1_kva[l1idx];
751 * If the L1 slot matches the pmap's domain
752 * number, then invalidate it.
754 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
755 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
761 * Release the L2 descriptor table back to the pool cache.
763 #ifndef PMAP_INCLUDE_PTE_SYNC
764 pmap_free_l2_ptp(ptep);
766 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
770 * Update the reference count in the associated l2_dtable
772 l2 = pm->pm_l2[L2_IDX(l1idx)];
773 if (--l2->l2_occupancy > 0)
777 * There are no more valid mappings in any of the Level 1
778 * slots managed by this l2_dtable. Go ahead and NULL-out
779 * the pointer in the parent pmap and free the l2_dtable.
781 pm->pm_l2[L2_IDX(l1idx)] = NULL;
782 uma_zfree(l2table_zone, l2);
786 * Pool cache constructors for L2 descriptor tables, metadata and pmap
790 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
792 #ifndef PMAP_INCLUDE_PTE_SYNC
793 struct l2_bucket *l2b;
794 pt_entry_t *ptep, pte;
796 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
799 * The mappings for these page tables were initially made using
800 * pmap_kenter() by the pool subsystem. Therefore, the cache-
801 * mode will not be right for page table mappings. To avoid
802 * polluting the pmap_kenter() code with a special case for
803 * page tables, we simply fix up the cache-mode here if it's not
806 l2b = pmap_get_l2_bucket(kernel_pmap, va);
807 ptep = &l2b->l2b_kva[l2pte_index(va)];
810 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
812 * Page tables must have the cache-mode set to
815 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
817 cpu_tlb_flushD_SE(va);
821 memset(mem, 0, L2_TABLE_SIZE_REAL);
822 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
827 * A bunch of routines to conditionally flush the caches/TLB depending
828 * on whether the specified pmap actually needs to be flushed at any
831 static PMAP_INLINE void
832 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
835 if (pmap_is_current(pm))
836 cpu_tlb_flushID_SE(va);
839 static PMAP_INLINE void
840 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
843 if (pmap_is_current(pm))
844 cpu_tlb_flushD_SE(va);
847 static PMAP_INLINE void
848 pmap_tlb_flushID(pmap_t pm)
851 if (pmap_is_current(pm))
854 static PMAP_INLINE void
855 pmap_tlb_flushD(pmap_t pm)
858 if (pmap_is_current(pm))
863 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
868 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
869 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
875 static PMAP_INLINE void
876 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
880 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
881 " len 0x%x ", pm, pm == kernel_pmap, va, len);
883 if (pmap_is_current(pm) || pm == kernel_pmap) {
884 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
886 if (pmap_has_valid_mapping(pm, va)) {
887 cpu_idcache_wbinv_range(va, rest);
888 cpu_l2cache_wbinv_range(va, rest);
892 rest = MIN(PAGE_SIZE, len);
897 static PMAP_INLINE void
898 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
903 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
904 "len 0x%x ", pm, pm == kernel_pmap, va, len);
905 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
907 if (pmap_is_current(pm)) {
908 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
910 if (pmap_has_valid_mapping(pm, va)) {
911 if (do_inv && rd_only) {
912 cpu_dcache_inv_range(va, rest);
913 cpu_l2cache_inv_range(va, rest);
915 cpu_dcache_wbinv_range(va, rest);
916 cpu_l2cache_wbinv_range(va, rest);
917 } else if (!rd_only) {
918 cpu_dcache_wb_range(va, rest);
919 cpu_l2cache_wb_range(va, rest);
925 rest = MIN(PAGE_SIZE, len);
930 static PMAP_INLINE void
931 pmap_idcache_wbinv_all(pmap_t pm)
934 if (pmap_is_current(pm)) {
935 cpu_idcache_wbinv_all();
936 cpu_l2cache_wbinv_all();
941 static PMAP_INLINE void
942 pmap_dcache_wbinv_all(pmap_t pm)
945 if (pmap_is_current(pm)) {
946 cpu_dcache_wbinv_all();
947 cpu_l2cache_wbinv_all();
955 * Make sure the pte is written out to RAM.
956 * We need to do this for one of two cases:
957 * - We're dealing with the kernel pmap
958 * - There is no pmap active in the cache/tlb.
959 * - The specified pmap is 'active' in the cache/tlb.
961 #ifdef PMAP_INCLUDE_PTE_SYNC
962 #define PTE_SYNC_CURRENT(pm, ptep) \
964 if (PMAP_NEEDS_PTE_SYNC && \
965 pmap_is_current(pm)) \
967 } while (/*CONSTCOND*/0)
969 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
973 * cacheable == -1 means we must make the entry uncacheable, 1 means
977 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
979 struct l2_bucket *l2b;
980 pt_entry_t *ptep, pte;
982 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
983 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
985 if (cacheable == 1) {
986 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
987 if (l2pte_valid(pte)) {
988 if (PV_BEEN_EXECD(pv->pv_flags)) {
989 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
990 } else if (PV_BEEN_REFD(pv->pv_flags)) {
991 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
995 pte = *ptep &~ L2_S_CACHE_MASK;
996 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
998 if (PV_BEEN_EXECD(pv->pv_flags)) {
999 pmap_idcache_wbinv_range(pv->pv_pmap,
1000 pv->pv_va, PAGE_SIZE);
1001 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1002 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1003 pmap_dcache_wb_range(pv->pv_pmap,
1004 pv->pv_va, PAGE_SIZE, TRUE,
1005 (pv->pv_flags & PVF_WRITE) == 0);
1006 pmap_tlb_flushD_SE(pv->pv_pmap,
1012 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1016 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1019 int writable = 0, kwritable = 0, uwritable = 0;
1020 int entries = 0, kentries = 0, uentries = 0;
1021 struct pv_entry *pv;
1023 rw_assert(&pvh_global_lock, RA_WLOCKED);
1025 /* the cache gets written back/invalidated on context switch.
1026 * therefore, if a user page shares an entry in the same page or
1027 * with the kernel map and at least one is writable, then the
1028 * cache entry must be set write-through.
1031 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1032 /* generate a count of the pv_entry uses */
1033 if (pv->pv_flags & PVF_WRITE) {
1034 if (pv->pv_pmap == kernel_pmap)
1036 else if (pv->pv_pmap == pm)
1040 if (pv->pv_pmap == kernel_pmap)
1043 if (pv->pv_pmap == pm)
1049 * check if the user duplicate mapping has
1052 if ((pm != kernel_pmap) && (((uentries > 1) && uwritable) ||
1056 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1057 /* check for user uncachable conditions - order is important */
1058 if (pm != kernel_pmap &&
1059 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap)) {
1061 if ((uentries > 1 && uwritable) || uwritable > 1) {
1063 /* user duplicate mapping */
1064 if (pv->pv_pmap != kernel_pmap)
1065 pv->pv_flags |= PVF_MWC;
1067 if (!(pv->pv_flags & PVF_NC)) {
1068 pv->pv_flags |= PVF_NC;
1069 pmap_set_cache_entry(pv, pm, va, -1);
1072 } else /* no longer a duplicate user */
1073 pv->pv_flags &= ~PVF_MWC;
1077 * check for kernel uncachable conditions
1078 * kernel writable or kernel readable with writable user entry
1080 if ((kwritable && (entries || kentries > 1)) ||
1082 ((kwritable != writable) && kentries &&
1083 (pv->pv_pmap == kernel_pmap ||
1084 (pv->pv_flags & PVF_WRITE) ||
1085 (pv->pv_flags & PVF_MWC)))) {
1087 if (!(pv->pv_flags & PVF_NC)) {
1088 pv->pv_flags |= PVF_NC;
1089 pmap_set_cache_entry(pv, pm, va, -1);
1094 /* kernel and user are cachable */
1095 if ((pm == kernel_pmap) && !(pv->pv_flags & PVF_MWC) &&
1096 (pv->pv_flags & PVF_NC)) {
1098 pv->pv_flags &= ~PVF_NC;
1099 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1100 pmap_set_cache_entry(pv, pm, va, 1);
1103 /* user is no longer sharable and writable */
1104 if (pm != kernel_pmap &&
1105 (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap) &&
1106 !pmwc && (pv->pv_flags & PVF_NC)) {
1108 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1109 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1110 pmap_set_cache_entry(pv, pm, va, 1);
1114 if ((kwritable == 0) && (writable == 0)) {
1115 pg->md.pvh_attrs &= ~PVF_MOD;
1116 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1122 * Modify pte bits for all ptes corresponding to the given physical address.
1123 * We use `maskbits' rather than `clearbits' because we're always passing
1124 * constants and the latter would require an extra inversion at run-time.
1127 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1129 struct l2_bucket *l2b;
1130 struct pv_entry *pv;
1131 pt_entry_t *ptep, npte, opte;
1137 rw_wlock(&pvh_global_lock);
1139 if (maskbits & PVF_WRITE)
1140 maskbits |= PVF_MOD;
1142 * Clear saved attributes (modify, reference)
1144 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1146 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1147 rw_wunlock(&pvh_global_lock);
1152 * Loop over all current mappings setting/clearing as appropos
1154 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1157 oflags = pv->pv_flags;
1159 if (!(oflags & maskbits)) {
1160 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1161 if (pg->md.pv_memattr !=
1162 VM_MEMATTR_UNCACHEABLE) {
1164 l2b = pmap_get_l2_bucket(pm, va);
1165 ptep = &l2b->l2b_kva[l2pte_index(va)];
1166 *ptep |= pte_l2_s_cache_mode;
1170 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1174 pv->pv_flags &= ~maskbits;
1178 l2b = pmap_get_l2_bucket(pm, va);
1180 ptep = &l2b->l2b_kva[l2pte_index(va)];
1181 npte = opte = *ptep;
1183 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1184 if ((pv->pv_flags & PVF_NC)) {
1186 * Entry is not cacheable:
1188 * Don't turn caching on again if this is a
1189 * modified emulation. This would be
1190 * inconsistent with the settings created by
1191 * pmap_fix_cache(). Otherwise, it's safe
1192 * to re-enable caching.
1194 * There's no need to call pmap_fix_cache()
1195 * here: all pages are losing their write
1198 if (maskbits & PVF_WRITE) {
1199 if (pg->md.pv_memattr !=
1200 VM_MEMATTR_UNCACHEABLE)
1201 npte |= pte_l2_s_cache_mode;
1202 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1205 if (opte & L2_S_PROT_W) {
1208 * Entry is writable/cacheable: check if pmap
1209 * is current if it is flush it, otherwise it
1210 * won't be in the cache
1212 if (PV_BEEN_EXECD(oflags))
1213 pmap_idcache_wbinv_range(pm, pv->pv_va,
1216 if (PV_BEEN_REFD(oflags))
1217 pmap_dcache_wb_range(pm, pv->pv_va,
1219 (maskbits & PVF_REF) ? TRUE : FALSE,
1223 /* make the pte read only */
1224 npte &= ~L2_S_PROT_W;
1227 if (maskbits & PVF_REF) {
1228 if ((pv->pv_flags & PVF_NC) == 0 &&
1229 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1231 * Check npte here; we may have already
1232 * done the wbinv above, and the validity
1233 * of the PTE is the same for opte and
1236 if (npte & L2_S_PROT_W) {
1237 if (PV_BEEN_EXECD(oflags))
1238 pmap_idcache_wbinv_range(pm,
1239 pv->pv_va, PAGE_SIZE);
1241 if (PV_BEEN_REFD(oflags))
1242 pmap_dcache_wb_range(pm,
1243 pv->pv_va, PAGE_SIZE,
1246 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1247 /* XXXJRT need idcache_inv_range */
1248 if (PV_BEEN_EXECD(oflags))
1249 pmap_idcache_wbinv_range(pm,
1250 pv->pv_va, PAGE_SIZE);
1252 if (PV_BEEN_REFD(oflags))
1253 pmap_dcache_wb_range(pm,
1254 pv->pv_va, PAGE_SIZE,
1260 * Make the PTE invalid so that we will take a
1261 * page fault the next time the mapping is
1264 npte &= ~L2_TYPE_MASK;
1265 npte |= L2_TYPE_INV;
1272 /* Flush the TLB entry if a current pmap. */
1273 if (PV_BEEN_EXECD(oflags))
1274 pmap_tlb_flushID_SE(pm, pv->pv_va);
1276 if (PV_BEEN_REFD(oflags))
1277 pmap_tlb_flushD_SE(pm, pv->pv_va);
1284 if (maskbits & PVF_WRITE)
1285 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1286 rw_wunlock(&pvh_global_lock);
1291 * main pv_entry manipulation functions:
1292 * pmap_enter_pv: enter a mapping onto a vm_page list
1293 * pmap_remove_pv: remove a mappiing from a vm_page list
1295 * NOTE: pmap_enter_pv expects to lock the pvh itself
1296 * pmap_remove_pv expects the caller to lock the pvh before calling
1300 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1302 * => caller should hold the proper lock on pvh_global_lock
1303 * => caller should have pmap locked
1304 * => we will (someday) gain the lock on the vm_page's PV list
1305 * => caller should adjust ptp's wire_count before calling
1306 * => caller should not adjust pmap's wire_count
1309 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1310 vm_offset_t va, u_int flags)
1313 rw_assert(&pvh_global_lock, RA_WLOCKED);
1314 PMAP_ASSERT_LOCKED(pm);
1315 if (pg->md.pv_kva != 0) {
1316 pve->pv_pmap = kernel_pmap;
1317 pve->pv_va = pg->md.pv_kva;
1318 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1319 if (pm != kernel_pmap)
1320 PMAP_LOCK(kernel_pmap);
1321 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1322 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1323 if (pm != kernel_pmap)
1324 PMAP_UNLOCK(kernel_pmap);
1326 if ((pve = pmap_get_pv_entry()) == NULL)
1327 panic("pmap_kenter_pv: no pv entries");
1331 pve->pv_flags = flags;
1332 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1333 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1334 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1335 if (pve->pv_flags & PVF_WIRED)
1336 ++pm->pm_stats.wired_count;
1337 vm_page_aflag_set(pg, PGA_REFERENCED);
1342 * pmap_find_pv: Find a pv entry
1344 * => caller should hold lock on vm_page
1346 static PMAP_INLINE struct pv_entry *
1347 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1349 struct pv_entry *pv;
1351 rw_assert(&pvh_global_lock, RA_WLOCKED);
1352 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1353 if (pm == pv->pv_pmap && va == pv->pv_va)
1359 * vector_page_setprot:
1361 * Manipulate the protection of the vector page.
1364 vector_page_setprot(int prot)
1366 struct l2_bucket *l2b;
1369 l2b = pmap_get_l2_bucket(kernel_pmap, vector_page);
1371 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1373 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1375 cpu_tlb_flushD_SE(vector_page);
1380 * pmap_remove_pv: try to remove a mapping from a pv_list
1382 * => caller should hold proper lock on pmap_main_lock
1383 * => pmap should be locked
1384 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1385 * => caller should adjust ptp's wire_count and free PTP if needed
1386 * => caller should NOT adjust pmap's wire_count
1387 * => we return the removed pve
1391 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1394 struct pv_entry *pv;
1395 rw_assert(&pvh_global_lock, RA_WLOCKED);
1396 PMAP_ASSERT_LOCKED(pm);
1397 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1398 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1399 if (pve->pv_flags & PVF_WIRED)
1400 --pm->pm_stats.wired_count;
1401 if (pg->md.pvh_attrs & PVF_MOD)
1403 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1404 pg->md.pvh_attrs &= ~PVF_REF;
1406 vm_page_aflag_set(pg, PGA_REFERENCED);
1407 if ((pve->pv_flags & PVF_NC) && ((pm == kernel_pmap) ||
1408 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1409 pmap_fix_cache(pg, pm, 0);
1410 else if (pve->pv_flags & PVF_WRITE) {
1411 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1412 if (pve->pv_flags & PVF_WRITE)
1415 pg->md.pvh_attrs &= ~PVF_MOD;
1416 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1419 pv = TAILQ_FIRST(&pg->md.pv_list);
1420 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1421 TAILQ_NEXT(pv, pv_list) == NULL) {
1423 pg->md.pv_kva = pv->pv_va;
1424 /* a recursive pmap_nuke_pv */
1425 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1426 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1427 if (pv->pv_flags & PVF_WIRED)
1428 --pm->pm_stats.wired_count;
1429 pg->md.pvh_attrs &= ~PVF_REF;
1430 pg->md.pvh_attrs &= ~PVF_MOD;
1431 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1432 pmap_free_pv_entry(pv);
1436 static struct pv_entry *
1437 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1439 struct pv_entry *pve;
1441 rw_assert(&pvh_global_lock, RA_WLOCKED);
1442 pve = TAILQ_FIRST(&pg->md.pv_list);
1445 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1446 pmap_nuke_pv(pg, pm, pve);
1449 pve = TAILQ_NEXT(pve, pv_list);
1452 if (pve == NULL && pg->md.pv_kva == va)
1455 return(pve); /* return removed pve */
1459 * pmap_modify_pv: Update pv flags
1461 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1462 * => caller should NOT adjust pmap's wire_count
1463 * => we return the old flags
1465 * Modify a physical-virtual mapping in the pv table
1468 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1469 u_int clr_mask, u_int set_mask)
1471 struct pv_entry *npv;
1472 u_int flags, oflags;
1474 PMAP_ASSERT_LOCKED(pm);
1475 rw_assert(&pvh_global_lock, RA_WLOCKED);
1476 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1480 * There is at least one VA mapping this page.
1483 if (clr_mask & (PVF_REF | PVF_MOD))
1484 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1486 oflags = npv->pv_flags;
1487 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1489 if ((flags ^ oflags) & PVF_WIRED) {
1490 if (flags & PVF_WIRED)
1491 ++pm->pm_stats.wired_count;
1493 --pm->pm_stats.wired_count;
1496 if ((flags ^ oflags) & PVF_WRITE)
1497 pmap_fix_cache(pg, pm, 0);
1502 /* Function to set the debug level of the pmap code */
1505 pmap_debug(int level)
1507 pmap_debug_level = level;
1508 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1510 #endif /* PMAP_DEBUG */
1513 pmap_pinit0(struct pmap *pmap)
1515 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1517 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1518 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1519 PMAP_LOCK_INIT(pmap);
1523 * Initialize a vm_page's machine-dependent fields.
1526 pmap_page_init(vm_page_t m)
1529 TAILQ_INIT(&m->md.pv_list);
1530 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1531 m->md.pvh_attrs = 0;
1536 * Initialize the pmap module.
1537 * Called by vm_init, to initialize any structures that the pmap
1538 * system needs to map virtual memory.
1543 int shpgperproc = PMAP_SHPGPERPROC;
1545 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1546 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1547 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1548 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1551 * Initialize the PV entry allocator.
1553 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1554 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1555 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1556 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1557 uma_zone_reserve_kva(pvzone, pv_entry_max);
1558 pv_entry_high_water = 9 * (pv_entry_max / 10);
1561 * Now it is safe to enable pv_table recording.
1563 PDEBUG(1, printf("pmap_init: done!\n"));
1567 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1569 struct l2_dtable *l2;
1570 struct l2_bucket *l2b;
1571 pd_entry_t *pl1pd, l1pd;
1572 pt_entry_t *ptep, pte;
1578 rw_wlock(&pvh_global_lock);
1582 * If there is no l2_dtable for this address, then the process
1583 * has no business accessing it.
1585 * Note: This will catch userland processes trying to access
1588 l2 = pm->pm_l2[L2_IDX(l1idx)];
1593 * Likewise if there is no L2 descriptor table
1595 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1596 if (l2b->l2b_kva == NULL)
1600 * Check the PTE itself.
1602 ptep = &l2b->l2b_kva[l2pte_index(va)];
1608 * Catch a userland access to the vector page mapped at 0x0
1610 if (user && (pte & L2_S_PROT_U) == 0)
1612 if (va == vector_page)
1617 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1619 * This looks like a good candidate for "page modified"
1622 struct pv_entry *pv;
1625 /* Extract the physical address of the page */
1626 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1629 /* Get the current flags for this page. */
1631 pv = pmap_find_pv(pg, pm, va);
1637 * Do the flags say this page is writable? If not then it
1638 * is a genuine write fault. If yes then the write fault is
1639 * our fault as we did not reflect the write access in the
1640 * PTE. Now we know a write has occurred we can correct this
1641 * and also set the modified bit
1643 if ((pv->pv_flags & PVF_WRITE) == 0) {
1647 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1649 pv->pv_flags |= PVF_REF | PVF_MOD;
1652 * Re-enable write permissions for the page. No need to call
1653 * pmap_fix_cache(), since this is just a
1654 * modified-emulation fault, and the PVF_WRITE bit isn't
1655 * changing. We've already set the cacheable bits based on
1656 * the assumption that we can write to this page.
1658 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1662 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1664 * This looks like a good candidate for "page referenced"
1667 struct pv_entry *pv;
1670 /* Extract the physical address of the page */
1671 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1673 /* Get the current flags for this page. */
1675 pv = pmap_find_pv(pg, pm, va);
1679 pg->md.pvh_attrs |= PVF_REF;
1680 pv->pv_flags |= PVF_REF;
1683 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1689 * We know there is a valid mapping here, so simply
1690 * fix up the L1 if necessary.
1692 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1693 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1694 if (*pl1pd != l1pd) {
1702 * If 'rv == 0' at this point, it generally indicates that there is a
1703 * stale TLB entry for the faulting address. This happens when two or
1704 * more processes are sharing an L1. Since we don't flush the TLB on
1705 * a context switch between such processes, we can take domain faults
1706 * for mappings which exist at the same VA in both processes. EVEN IF
1707 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1710 * This is extremely likely to happen if pmap_enter() updated the L1
1711 * entry for a recently entered mapping. In this case, the TLB is
1712 * flushed for the new mapping, but there may still be TLB entries for
1713 * other mappings belonging to other processes in the 1MB range
1714 * covered by the L1 entry.
1716 * Since 'rv == 0', we know that the L1 already contains the correct
1717 * value, so the fault must be due to a stale TLB entry.
1719 * Since we always need to flush the TLB anyway in the case where we
1720 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1721 * stale TLB entries dynamically.
1723 * However, the above condition can ONLY happen if the current L1 is
1724 * being shared. If it happens when the L1 is unshared, it indicates
1725 * that other parts of the pmap are not doing their job WRT managing
1728 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
1729 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
1730 pm, (u_long)va, ftype);
1731 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1732 l2, l2b, ptep, pl1pd);
1733 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1734 pte, l1pd, last_fault_code);
1741 cpu_tlb_flushID_SE(va);
1747 rw_wunlock(&pvh_global_lock);
1755 struct l2_bucket *l2b;
1756 struct l1_ttable *l1;
1758 pt_entry_t *ptep, pte;
1759 vm_offset_t va, eva;
1762 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1764 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1766 for (loop = 0; loop < needed; loop++, l1++) {
1767 /* Allocate a L1 page table */
1768 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1769 0xffffffff, L1_TABLE_SIZE, 0);
1772 panic("Cannot allocate L1 KVM");
1774 eva = va + L1_TABLE_SIZE;
1775 pl1pt = (pd_entry_t *)va;
1778 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1779 ptep = &l2b->l2b_kva[l2pte_index(va)];
1781 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1784 cpu_tlb_flushD_SE(va);
1788 pmap_init_l1(l1, pl1pt);
1793 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1799 * This is used to stuff certain critical values into the PCB where they
1800 * can be accessed quickly from cpu_switch() et al.
1803 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
1805 struct l2_bucket *l2b;
1807 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
1808 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
1809 (DOMAIN_CLIENT << (pm->pm_domain * 2));
1811 if (vector_page < KERNBASE) {
1812 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
1813 l2b = pmap_get_l2_bucket(pm, vector_page);
1814 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
1815 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
1817 pcb->pcb_pl1vec = NULL;
1821 pmap_activate(struct thread *td)
1826 pm = vmspace_pmap(td->td_proc->p_vmspace);
1830 pmap_set_pcb_pagedir(pm, pcb);
1832 if (td == curthread) {
1833 u_int cur_dacr, cur_ttb;
1835 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
1836 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
1838 cur_ttb &= ~(L1_TABLE_SIZE - 1);
1840 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
1841 cur_dacr == pcb->pcb_dacr) {
1843 * No need to switch address spaces.
1851 * We MUST, I repeat, MUST fix up the L1 entry corresponding
1852 * to 'vector_page' in the incoming L1 table before switching
1853 * to it otherwise subsequent interrupts/exceptions (including
1854 * domain faults!) will jump into hyperspace.
1856 if (pcb->pcb_pl1vec) {
1858 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1860 * Don't need to PTE_SYNC() at this point since
1861 * cpu_setttb() is about to flush both the cache
1866 cpu_domains(pcb->pcb_dacr);
1867 cpu_setttb(pcb->pcb_pagedir);
1873 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
1875 pd_entry_t *pdep, pde;
1876 pt_entry_t *ptep, pte;
1881 * Make sure the descriptor itself has the correct cache mode
1883 pdep = &kl1[L1_IDX(va)];
1886 if (l1pte_section_p(pde)) {
1887 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
1888 *pdep = (pde & ~L1_S_CACHE_MASK) |
1889 pte_l1_s_cache_mode_pt;
1891 cpu_dcache_wbinv_range((vm_offset_t)pdep,
1893 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
1898 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1899 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1901 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
1903 ptep = &ptep[l2pte_index(va)];
1905 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1906 *ptep = (pte & ~L2_S_CACHE_MASK) |
1907 pte_l2_s_cache_mode_pt;
1909 cpu_dcache_wbinv_range((vm_offset_t)ptep,
1911 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
1921 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
1924 vm_offset_t va = *availp;
1925 struct l2_bucket *l2b;
1928 l2b = pmap_get_l2_bucket(kernel_pmap, va);
1930 panic("pmap_alloc_specials: no l2b for 0x%x", va);
1932 *ptep = &l2b->l2b_kva[l2pte_index(va)];
1936 *availp = va + (PAGE_SIZE * pages);
1940 * Bootstrap the system enough to run with virtual memory.
1942 * On the arm this is called after mapping has already been enabled
1943 * and just syncs the pmap module with what has already been done.
1944 * [We can't call it easily with mapping off since the kernel is not
1945 * mapped with PA == VA, hence we would have to relocate every address
1946 * from the linked base (virtual) address "KERNBASE" to the actual
1947 * (physical) address starting relative to 0]
1949 #define PMAP_STATIC_L2_SIZE 16
1951 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
1953 static struct l1_ttable static_l1;
1954 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
1955 struct l1_ttable *l1 = &static_l1;
1956 struct l2_dtable *l2;
1957 struct l2_bucket *l2b;
1959 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
1961 pt_entry_t *qmap_pte;
1965 int l1idx, l2idx, l2next = 0;
1967 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
1968 firstaddr, vm_max_kernel_address));
1970 virtual_avail = firstaddr;
1971 kernel_pmap->pm_l1 = l1;
1972 kernel_l1pa = l1pt->pv_pa;
1975 * Scan the L1 translation table created by initarm() and create
1976 * the required metadata for all valid mappings found in it.
1978 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
1979 pde = kernel_l1pt[l1idx];
1982 * We're only interested in Coarse mappings.
1983 * pmap_extract() can deal with section mappings without
1984 * recourse to checking L2 metadata.
1986 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
1990 * Lookup the KVA of this L2 descriptor table
1992 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1993 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1996 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
1997 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2001 * Fetch the associated L2 metadata structure.
2002 * Allocate a new one if necessary.
2004 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2005 if (l2next == PMAP_STATIC_L2_SIZE)
2006 panic("pmap_bootstrap: out of static L2s");
2007 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2008 &static_l2[l2next++];
2012 * One more L1 slot tracked...
2017 * Fill in the details of the L2 descriptor in the
2018 * appropriate bucket.
2020 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2021 l2b->l2b_kva = ptep;
2023 l2b->l2b_l1idx = l1idx;
2026 * Establish an initial occupancy count for this descriptor
2029 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2031 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2032 l2b->l2b_occupancy++;
2037 * Make sure the descriptor itself has the correct cache mode.
2038 * If not, fix it, but whine about the problem. Port-meisters
2039 * should consider this a clue to fix up their initarm()
2042 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2043 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2044 "L2 pte @ %p\n", ptep);
2050 * Ensure the primary (kernel) L1 has the correct cache mode for
2051 * a page table. Bitch if it is not correctly set.
2053 for (va = (vm_offset_t)kernel_l1pt;
2054 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2055 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2056 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2057 "primary L1 @ 0x%x\n", va);
2060 cpu_dcache_wbinv_all();
2061 cpu_l2cache_wbinv_all();
2065 PMAP_LOCK_INIT(kernel_pmap);
2066 CPU_FILL(&kernel_pmap->pm_active);
2067 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2068 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2071 * Initialize the global pv list lock.
2073 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2076 * Reserve some special page table entries/VA space for temporary
2079 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2080 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2081 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2082 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2083 pmap_alloc_specials(&virtual_avail, 1, &qmap_addr, &qmap_pte);
2084 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)qmap_pte);
2085 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2087 pmap_alloc_specials(&virtual_avail,
2088 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2089 &pmap_kernel_l2ptp_kva, NULL);
2091 size = howmany(size, L2_BUCKET_SIZE);
2092 pmap_alloc_specials(&virtual_avail,
2093 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2094 &pmap_kernel_l2dtable_kva, NULL);
2096 pmap_alloc_specials(&virtual_avail,
2097 1, (vm_offset_t*)&_tmppt, NULL);
2098 pmap_alloc_specials(&virtual_avail,
2099 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2100 SLIST_INIT(&l1_list);
2101 TAILQ_INIT(&l1_lru_list);
2102 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2103 pmap_init_l1(l1, kernel_l1pt);
2104 cpu_dcache_wbinv_all();
2105 cpu_l2cache_wbinv_all();
2107 virtual_avail = round_page(virtual_avail);
2108 virtual_end = vm_max_kernel_address;
2109 kernel_vm_end = pmap_curmaxkvaddr;
2110 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2111 mtx_init(&qmap_mtx, "quick mapping mtx", NULL, MTX_DEF);
2113 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2116 /***************************************************
2117 * Pmap allocation/deallocation routines.
2118 ***************************************************/
2121 * Release any resources held by the given physical map.
2122 * Called when a pmap initialized by pmap_pinit is being released.
2123 * Should only be called if the map contains no valid mappings.
2126 pmap_release(pmap_t pmap)
2130 pmap_idcache_wbinv_all(pmap);
2131 cpu_l2cache_wbinv_all();
2132 pmap_tlb_flushID(pmap);
2134 if (vector_page < KERNBASE) {
2135 struct pcb *curpcb = PCPU_GET(curpcb);
2136 pcb = thread0.td_pcb;
2137 if (pmap_is_current(pmap)) {
2139 * Frob the L1 entry corresponding to the vector
2140 * page so that it contains the kernel pmap's domain
2141 * number. This will ensure pmap_remove() does not
2142 * pull the current vector page out from under us.
2145 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2146 cpu_domains(pcb->pcb_dacr);
2147 cpu_setttb(pcb->pcb_pagedir);
2150 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2152 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2153 * since this process has no remaining mappings of its own.
2155 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2156 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2157 curpcb->pcb_dacr = pcb->pcb_dacr;
2158 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2163 dprintf("pmap_release()\n");
2169 * Helper function for pmap_grow_l2_bucket()
2172 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2174 struct l2_bucket *l2b;
2179 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2182 pa = VM_PAGE_TO_PHYS(pg);
2187 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2189 ptep = &l2b->l2b_kva[l2pte_index(va)];
2190 *ptep = L2_S_PROTO | pa | cache_mode |
2191 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2197 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2198 * used by pmap_growkernel().
2200 static __inline struct l2_bucket *
2201 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2203 struct l2_dtable *l2;
2204 struct l2_bucket *l2b;
2205 struct l1_ttable *l1;
2212 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2214 * No mapping at this address, as there is
2215 * no entry in the L1 table.
2216 * Need to allocate a new l2_dtable.
2218 nva = pmap_kernel_l2dtable_kva;
2219 if ((nva & PAGE_MASK) == 0) {
2221 * Need to allocate a backing page
2223 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2227 l2 = (struct l2_dtable *)nva;
2228 nva += sizeof(struct l2_dtable);
2230 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2233 * The new l2_dtable straddles a page boundary.
2234 * Map in another page to cover it.
2236 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2240 pmap_kernel_l2dtable_kva = nva;
2243 * Link it into the parent pmap
2245 pm->pm_l2[L2_IDX(l1idx)] = l2;
2246 memset(l2, 0, sizeof(*l2));
2249 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2252 * Fetch pointer to the L2 page table associated with the address.
2254 if (l2b->l2b_kva == NULL) {
2258 * No L2 page table has been allocated. Chances are, this
2259 * is because we just allocated the l2_dtable, above.
2261 nva = pmap_kernel_l2ptp_kva;
2262 ptep = (pt_entry_t *)nva;
2263 if ((nva & PAGE_MASK) == 0) {
2265 * Need to allocate a backing page
2267 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2268 &pmap_kernel_l2ptp_phys))
2270 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2272 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2274 l2b->l2b_kva = ptep;
2275 l2b->l2b_l1idx = l1idx;
2276 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2278 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2279 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2282 /* Distribute new L1 entry to all other L1s */
2283 SLIST_FOREACH(l1, &l1_list, l1_link) {
2284 pl1pd = &l1->l1_kva[L1_IDX(va)];
2285 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2295 * grow the number of kernel page table entries, if needed
2298 pmap_growkernel(vm_offset_t addr)
2300 pmap_t kpm = kernel_pmap;
2302 if (addr <= pmap_curmaxkvaddr)
2303 return; /* we are OK */
2306 * whoops! we need to add kernel PTPs
2309 /* Map 1MB at a time */
2310 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2311 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2314 * flush out the cache, expensive but growkernel will happen so
2317 cpu_dcache_wbinv_all();
2318 cpu_l2cache_wbinv_all();
2321 kernel_vm_end = pmap_curmaxkvaddr;
2326 * Remove all pages from specified address space
2327 * this aids process exit speeds. Also, this code
2328 * is special cased for current process only, but
2329 * can have the more generic (and slightly slower)
2330 * mode enabled. This is much faster than pmap_remove
2331 * in the case of running down an entire address space.
2334 pmap_remove_pages(pmap_t pmap)
2336 struct pv_entry *pv, *npv;
2337 struct l2_bucket *l2b = NULL;
2341 rw_wlock(&pvh_global_lock);
2343 cpu_idcache_wbinv_all();
2344 cpu_l2cache_wbinv_all();
2345 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2346 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2347 /* Cannot remove wired or unmanaged pages now. */
2348 npv = TAILQ_NEXT(pv, pv_plist);
2351 pmap->pm_stats.resident_count--;
2352 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2353 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2354 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2355 m = PHYS_TO_VM_PAGE(*pt & L2_S_FRAME);
2356 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2359 npv = TAILQ_NEXT(pv, pv_plist);
2360 pmap_nuke_pv(m, pmap, pv);
2361 if (TAILQ_EMPTY(&m->md.pv_list))
2362 vm_page_aflag_clear(m, PGA_WRITEABLE);
2363 pmap_free_pv_entry(pv);
2364 pmap_free_l2_bucket(pmap, l2b, 1);
2366 rw_wunlock(&pvh_global_lock);
2373 /***************************************************
2374 * Low level mapping routines.....
2375 ***************************************************/
2377 /* Map a section into the KVA. */
2380 * Make a temporary mapping for a physical address. This is only intended
2381 * to be used for panic dumps.
2384 pmap_kenter_temporary(vm_paddr_t pa, int i)
2388 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2389 pmap_kenter(va, pa);
2390 return ((void *)crashdumpmap);
2394 * add a wired page to the kva
2395 * note that in order for the mapping to take effect -- you
2396 * should do a invltlb after doing the pmap_kenter...
2398 static PMAP_INLINE void
2399 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2401 struct l2_bucket *l2b;
2404 struct pv_entry *pve;
2407 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2408 (uint32_t) va, (uint32_t) pa));
2411 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2413 l2b = pmap_grow_l2_bucket(kernel_pmap, va);
2414 KASSERT(l2b != NULL, ("No L2 Bucket"));
2415 pte = &l2b->l2b_kva[l2pte_index(va)];
2417 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2418 (uint32_t) pte, opte, *pte));
2419 if (l2pte_valid(opte)) {
2423 l2b->l2b_occupancy++;
2425 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2426 VM_PROT_READ | VM_PROT_WRITE);
2427 if (flags & KENTER_CACHE)
2428 *pte |= pte_l2_s_cache_mode;
2429 if (flags & KENTER_USER)
2430 *pte |= L2_S_PROT_U;
2434 * A kernel mapping may not be the page's only mapping, so create a PV
2435 * entry to ensure proper caching.
2437 * The existence test for the pvzone is used to delay the recording of
2438 * kernel mappings until the VM system is fully initialized.
2440 * This expects the physical memory to have a vm_page_array entry.
2442 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2443 rw_wlock(&pvh_global_lock);
2444 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2445 if ((pve = pmap_get_pv_entry()) == NULL)
2446 panic("pmap_kenter_internal: no pv entries");
2447 PMAP_LOCK(kernel_pmap);
2448 pmap_enter_pv(m, pve, kernel_pmap, va,
2449 PVF_WRITE | PVF_UNMAN);
2450 pmap_fix_cache(m, kernel_pmap, va);
2451 PMAP_UNLOCK(kernel_pmap);
2455 rw_wunlock(&pvh_global_lock);
2460 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2462 pmap_kenter_internal(va, pa, KENTER_CACHE);
2466 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2469 pmap_kenter_internal(va, pa, 0);
2473 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
2477 KASSERT((size & PAGE_MASK) == 0,
2478 ("%s: device mapping not page-sized", __func__));
2482 pmap_kenter_internal(va, pa, 0);
2490 pmap_kremove_device(vm_offset_t va, vm_size_t size)
2494 KASSERT((size & PAGE_MASK) == 0,
2495 ("%s: device mapping not page-sized", __func__));
2506 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2509 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2511 * Call pmap_fault_fixup now, to make sure we'll have no exception
2512 * at the first use of the new address, or bad things will happen,
2513 * as we use one of these addresses in the exception handlers.
2515 pmap_fault_fixup(kernel_pmap, va, VM_PROT_READ|VM_PROT_WRITE, 1);
2519 pmap_kextract(vm_offset_t va)
2522 return (pmap_extract_locked(kernel_pmap, va));
2526 * remove a page from the kernel pagetables
2529 pmap_kremove(vm_offset_t va)
2531 struct l2_bucket *l2b;
2532 pt_entry_t *pte, opte;
2533 struct pv_entry *pve;
2537 l2b = pmap_get_l2_bucket(kernel_pmap, va);
2540 KASSERT(l2b != NULL, ("No L2 Bucket"));
2541 pte = &l2b->l2b_kva[l2pte_index(va)];
2543 if (l2pte_valid(opte)) {
2544 /* pa = vtophs(va) taken from pmap_extract() */
2545 if ((opte & L2_TYPE_MASK) == L2_TYPE_L)
2546 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2548 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2549 /* note: should never have to remove an allocation
2550 * before the pvzone is initialized.
2552 rw_wlock(&pvh_global_lock);
2553 PMAP_LOCK(kernel_pmap);
2554 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2555 (pve = pmap_remove_pv(m, kernel_pmap, va)))
2556 pmap_free_pv_entry(pve);
2557 PMAP_UNLOCK(kernel_pmap);
2558 rw_wunlock(&pvh_global_lock);
2559 va = va & ~PAGE_MASK;
2560 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2561 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2562 cpu_tlb_flushD_SE(va);
2570 * Used to map a range of physical addresses into kernel
2571 * virtual address space.
2573 * The value passed in '*virt' is a suggested virtual address for
2574 * the mapping. Architectures which can support a direct-mapped
2575 * physical to virtual region can return the appropriate address
2576 * within that region, leaving '*virt' unchanged. Other
2577 * architectures should map the pages starting at '*virt' and
2578 * update '*virt' with the first usable address after the mapped
2582 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2584 vm_offset_t sva = *virt;
2585 vm_offset_t va = sva;
2587 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2588 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2591 while (start < end) {
2592 pmap_kenter(va, start);
2601 pmap_wb_page(vm_page_t m)
2603 struct pv_entry *pv;
2605 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2606 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2607 (pv->pv_flags & PVF_WRITE) == 0);
2611 pmap_inv_page(vm_page_t m)
2613 struct pv_entry *pv;
2615 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2616 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2619 * Add a list of wired pages to the kva
2620 * this routine is only used for temporary
2621 * kernel mappings that do not need to have
2622 * page modification or references recorded.
2623 * Note that old mappings are simply written
2624 * over. The page *must* be wired.
2627 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2631 for (i = 0; i < count; i++) {
2633 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2641 * this routine jerks page mappings from the
2642 * kernel -- it is meant only for temporary mappings.
2645 pmap_qremove(vm_offset_t va, int count)
2650 for (i = 0; i < count; i++) {
2653 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2662 * pmap_object_init_pt preloads the ptes for a given object
2663 * into the specified pmap. This eliminates the blast of soft
2664 * faults on process startup and immediately after an mmap.
2667 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2668 vm_pindex_t pindex, vm_size_t size)
2671 VM_OBJECT_ASSERT_WLOCKED(object);
2672 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2673 ("pmap_object_init_pt: non-device object"));
2678 * pmap_is_prefaultable:
2680 * Return whether or not the specified virtual address is elgible
2684 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2689 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
2691 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
2698 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2699 * Returns TRUE if the mapping exists, else FALSE.
2701 * NOTE: This function is only used by a couple of arm-specific modules.
2702 * It is not safe to take any pmap locks here, since we could be right
2703 * in the middle of debugging the pmap anyway...
2705 * It is possible for this routine to return FALSE even though a valid
2706 * mapping does exist. This is because we don't lock, so the metadata
2707 * state may be inconsistent.
2709 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2710 * a "section" mapping.
2713 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
2715 struct l2_dtable *l2;
2716 pd_entry_t *pl1pd, l1pd;
2720 if (pm->pm_l1 == NULL)
2724 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
2727 if (l1pte_section_p(l1pd)) {
2732 if (pm->pm_l2 == NULL)
2735 l2 = pm->pm_l2[L2_IDX(l1idx)];
2738 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2742 *ptp = &ptep[l2pte_index(va)];
2747 * Routine: pmap_remove_all
2749 * Removes this physical page from
2750 * all physical maps in which it resides.
2751 * Reflects back modify bits to the pager.
2754 * Original versions of this routine were very
2755 * inefficient because they iteratively called
2756 * pmap_remove (slow...)
2759 pmap_remove_all(vm_page_t m)
2763 struct l2_bucket *l2b;
2764 boolean_t flush = FALSE;
2768 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2769 ("pmap_remove_all: page %p is not managed", m));
2770 if (TAILQ_EMPTY(&m->md.pv_list))
2772 rw_wlock(&pvh_global_lock);
2775 * XXX This call shouldn't exist. Iterating over the PV list twice,
2776 * once in pmap_clearbit() and again below, is both unnecessary and
2777 * inefficient. The below code should itself write back the cache
2778 * entry before it destroys the mapping.
2780 pmap_clearbit(m, PVF_WRITE);
2781 curpm = vmspace_pmap(curproc->p_vmspace);
2782 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2783 if (flush == FALSE && (pv->pv_pmap == curpm ||
2784 pv->pv_pmap == kernel_pmap))
2787 PMAP_LOCK(pv->pv_pmap);
2789 * Cached contents were written-back in pmap_clearbit(),
2790 * but we still have to invalidate the cache entry to make
2791 * sure stale data are not retrieved when another page will be
2792 * mapped under this virtual address.
2794 if (pmap_is_current(pv->pv_pmap)) {
2795 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
2796 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
2797 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
2800 if (pv->pv_flags & PVF_UNMAN) {
2801 /* remove the pv entry, but do not remove the mapping
2802 * and remember this is a kernel mapped page
2804 m->md.pv_kva = pv->pv_va;
2806 /* remove the mapping and pv entry */
2807 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
2808 KASSERT(l2b != NULL, ("No l2 bucket"));
2809 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2811 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
2812 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
2813 pv->pv_pmap->pm_stats.resident_count--;
2814 flags |= pv->pv_flags;
2816 pmap_nuke_pv(m, pv->pv_pmap, pv);
2817 PMAP_UNLOCK(pv->pv_pmap);
2818 pmap_free_pv_entry(pv);
2822 if (PV_BEEN_EXECD(flags))
2823 pmap_tlb_flushID(curpm);
2825 pmap_tlb_flushD(curpm);
2827 vm_page_aflag_clear(m, PGA_WRITEABLE);
2828 rw_wunlock(&pvh_global_lock);
2833 * Set the physical protection on the
2834 * specified range of this map as requested.
2837 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2839 struct l2_bucket *l2b;
2840 pt_entry_t *ptep, pte;
2841 vm_offset_t next_bucket;
2845 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
2846 pm, sva, eva, prot);
2848 if ((prot & VM_PROT_READ) == 0) {
2849 pmap_remove(pm, sva, eva);
2853 if (prot & VM_PROT_WRITE) {
2855 * If this is a read->write transition, just ignore it and let
2856 * vm_fault() take care of it later.
2861 rw_wlock(&pvh_global_lock);
2865 * OK, at this point, we know we're doing write-protect operation.
2866 * If the pmap is active, write-back the range.
2868 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
2870 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
2874 next_bucket = L2_NEXT_BUCKET(sva);
2875 if (next_bucket > eva)
2878 l2b = pmap_get_l2_bucket(pm, sva);
2884 ptep = &l2b->l2b_kva[l2pte_index(sva)];
2886 while (sva < next_bucket) {
2887 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
2891 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2892 pte &= ~L2_S_PROT_W;
2896 if (!(pg->oflags & VPO_UNMANAGED)) {
2897 f = pmap_modify_pv(pg, pm, sva,
2908 if (PV_BEEN_EXECD(f))
2909 pmap_tlb_flushID_SE(pm, sva);
2911 if (PV_BEEN_REFD(f))
2912 pmap_tlb_flushD_SE(pm, sva);
2922 if (PV_BEEN_EXECD(flags))
2923 pmap_tlb_flushID(pm);
2925 if (PV_BEEN_REFD(flags))
2926 pmap_tlb_flushD(pm);
2928 rw_wunlock(&pvh_global_lock);
2935 * Insert the given physical page (p) at
2936 * the specified virtual address (v) in the
2937 * target physical map with the protection requested.
2939 * If specified, the page will be wired down, meaning
2940 * that the related pte can not be reclaimed.
2942 * NB: This is the only routine which MAY NOT lazy-evaluate
2943 * or lose information. That is, this routine must actually
2944 * insert this page into the given map NOW.
2948 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2949 u_int flags, int8_t psind __unused)
2953 rw_wlock(&pvh_global_lock);
2955 rv = pmap_enter_locked(pmap, va, m, prot, flags);
2956 rw_wunlock(&pvh_global_lock);
2962 * The pvh global and pmap locks must be held.
2965 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2968 struct l2_bucket *l2b = NULL;
2969 struct vm_page *opg;
2970 struct pv_entry *pve = NULL;
2971 pt_entry_t *ptep, npte, opte;
2976 PMAP_ASSERT_LOCKED(pmap);
2977 rw_assert(&pvh_global_lock, RA_WLOCKED);
2978 if (va == vector_page) {
2979 pa = systempage.pv_pa;
2982 if ((m->oflags & VPO_UNMANAGED) == 0) {
2983 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0)
2984 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2986 VM_OBJECT_ASSERT_LOCKED(m->object);
2988 pa = VM_PAGE_TO_PHYS(m);
2991 if (prot & VM_PROT_WRITE)
2992 nflags |= PVF_WRITE;
2993 if (prot & VM_PROT_EXECUTE)
2995 if ((flags & PMAP_ENTER_WIRED) != 0)
2996 nflags |= PVF_WIRED;
2997 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
2998 "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags));
3000 if (pmap == kernel_pmap) {
3001 l2b = pmap_get_l2_bucket(pmap, va);
3003 l2b = pmap_grow_l2_bucket(pmap, va);
3006 l2b = pmap_alloc_l2_bucket(pmap, va);
3008 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3010 rw_wunlock(&pvh_global_lock);
3012 rw_wlock(&pvh_global_lock);
3016 return (KERN_RESOURCE_SHORTAGE);
3020 ptep = &l2b->l2b_kva[l2pte_index(va)];
3027 * There is already a mapping at this address.
3028 * If the physical address is different, lookup the
3031 if (l2pte_pa(opte) != pa)
3032 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3038 if ((prot & (VM_PROT_ALL)) ||
3039 (!m || m->md.pvh_attrs & PVF_REF)) {
3041 * - The access type indicates that we don't need
3042 * to do referenced emulation.
3044 * - The physical page has already been referenced
3045 * so no need to re-do referenced emulation here.
3051 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3052 (m->md.pvh_attrs & PVF_MOD))) {
3054 * This is a writable mapping, and the
3055 * page's mod state indicates it has
3056 * already been modified. Make it
3057 * writable from the outset.
3060 if (!(m->md.pvh_attrs & PVF_MOD))
3064 vm_page_aflag_set(m, PGA_REFERENCED);
3067 * Need to do page referenced emulation.
3069 npte |= L2_TYPE_INV;
3072 if (prot & VM_PROT_WRITE) {
3073 npte |= L2_S_PROT_W;
3075 (m->oflags & VPO_UNMANAGED) == 0)
3076 vm_page_aflag_set(m, PGA_WRITEABLE);
3078 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3079 npte |= pte_l2_s_cache_mode;
3080 if (m && m == opg) {
3082 * We're changing the attrs of an existing mapping.
3084 oflags = pmap_modify_pv(m, pmap, va,
3085 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3086 PVF_MOD | PVF_REF, nflags);
3089 * We may need to flush the cache if we're
3092 if (pmap_is_current(pmap) &&
3093 (oflags & PVF_NC) == 0 &&
3094 (opte & L2_S_PROT_W) != 0 &&
3095 (prot & VM_PROT_WRITE) == 0 &&
3096 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3097 cpu_dcache_wb_range(va, PAGE_SIZE);
3098 cpu_l2cache_wb_range(va, PAGE_SIZE);
3102 * New mapping, or changing the backing page
3103 * of an existing mapping.
3107 * Replacing an existing mapping with a new one.
3108 * It is part of our managed memory so we
3109 * must remove it from the PV list
3111 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3113 /* note for patch: the oflags/invalidation was moved
3114 * because PG_FICTITIOUS pages could free the pve
3116 oflags = pve->pv_flags;
3118 * If the old mapping was valid (ref/mod
3119 * emulation creates 'invalid' mappings
3120 * initially) then make sure to frob
3123 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3124 if (PV_BEEN_EXECD(oflags)) {
3125 pmap_idcache_wbinv_range(pmap, va,
3128 if (PV_BEEN_REFD(oflags)) {
3129 pmap_dcache_wb_range(pmap, va,
3131 (oflags & PVF_WRITE) == 0);
3135 /* free/allocate a pv_entry for UNMANAGED pages if
3136 * this physical page is not/is already mapped.
3139 if (m && (m->oflags & VPO_UNMANAGED) &&
3141 TAILQ_EMPTY(&m->md.pv_list)) {
3142 pmap_free_pv_entry(pve);
3146 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3147 !TAILQ_EMPTY(&m->md.pv_list)))
3148 pve = pmap_get_pv_entry();
3150 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3151 !TAILQ_EMPTY(&m->md.pv_list)))
3152 pve = pmap_get_pv_entry();
3155 if ((m->oflags & VPO_UNMANAGED)) {
3156 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3158 KASSERT(pve != NULL, ("No pv"));
3159 nflags |= PVF_UNMAN;
3160 pmap_enter_pv(m, pve, pmap, va, nflags);
3164 KASSERT(va < kmi.clean_sva ||
3165 va >= kmi.clean_eva,
3166 ("pmap_enter: managed mapping within the clean submap"));
3167 KASSERT(pve != NULL, ("No pv"));
3168 pmap_enter_pv(m, pve, pmap, va, nflags);
3173 * Make sure userland mappings get the right permissions
3175 if (pmap != kernel_pmap && va != vector_page) {
3176 npte |= L2_S_PROT_U;
3180 * Keep the stats up to date
3183 l2b->l2b_occupancy++;
3184 pmap->pm_stats.resident_count++;
3188 * If this is just a wiring change, the two PTEs will be
3189 * identical, so there's no need to update the page table.
3192 boolean_t is_cached = pmap_is_current(pmap);
3197 * We only need to frob the cache/tlb if this pmap
3201 if (L1_IDX(va) != L1_IDX(vector_page) &&
3202 l2pte_valid(npte)) {
3204 * This mapping is likely to be accessed as
3205 * soon as we return to userland. Fix up the
3206 * L1 entry to avoid taking another
3207 * page/domain fault.
3209 pd_entry_t *pl1pd, l1pd;
3211 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3212 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3214 if (*pl1pd != l1pd) {
3221 if (PV_BEEN_EXECD(oflags))
3222 pmap_tlb_flushID_SE(pmap, va);
3223 else if (PV_BEEN_REFD(oflags))
3224 pmap_tlb_flushD_SE(pmap, va);
3228 pmap_fix_cache(m, pmap, va);
3230 return (KERN_SUCCESS);
3234 * Maps a sequence of resident pages belonging to the same object.
3235 * The sequence begins with the given page m_start. This page is
3236 * mapped at the given virtual address start. Each subsequent page is
3237 * mapped at a virtual address that is offset from start by the same
3238 * amount as the page is offset from m_start within the object. The
3239 * last page in the sequence is the page with the largest offset from
3240 * m_start that can be mapped at a virtual address less than the given
3241 * virtual address end. Not every virtual page between start and end
3242 * is mapped; only those for which a resident page exists with the
3243 * corresponding offset from m_start are mapped.
3246 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3247 vm_page_t m_start, vm_prot_t prot)
3250 vm_pindex_t diff, psize;
3252 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3254 psize = atop(end - start);
3256 rw_wlock(&pvh_global_lock);
3258 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3259 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3260 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
3261 PMAP_ENTER_QUICK_LOCKED);
3262 m = TAILQ_NEXT(m, listq);
3264 rw_wunlock(&pvh_global_lock);
3269 * this code makes some *MAJOR* assumptions:
3270 * 1. Current pmap & pmap exists.
3273 * 4. No page table pages.
3274 * but is *MUCH* faster than pmap_enter...
3278 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3281 rw_wlock(&pvh_global_lock);
3283 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3284 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED);
3285 rw_wunlock(&pvh_global_lock);
3290 * Clear the wired attribute from the mappings for the specified range of
3291 * addresses in the given pmap. Every valid mapping within that range
3292 * must have the wired attribute set. In contrast, invalid mappings
3293 * cannot have the wired attribute set, so they are ignored.
3295 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3299 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3301 struct l2_bucket *l2b;
3302 pt_entry_t *ptep, pte;
3304 vm_offset_t next_bucket;
3307 rw_wlock(&pvh_global_lock);
3310 next_bucket = L2_NEXT_BUCKET(sva);
3311 if (next_bucket > eva)
3313 l2b = pmap_get_l2_bucket(pmap, sva);
3318 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3319 sva += PAGE_SIZE, ptep++) {
3320 if ((pte = *ptep) == 0 ||
3321 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3322 (m->oflags & VPO_UNMANAGED) != 0)
3324 pv = pmap_find_pv(m, pmap, sva);
3325 if ((pv->pv_flags & PVF_WIRED) == 0)
3326 panic("pmap_unwire: pv %p isn't wired", pv);
3327 pv->pv_flags &= ~PVF_WIRED;
3328 pmap->pm_stats.wired_count--;
3331 rw_wunlock(&pvh_global_lock);
3337 * Copy the range specified by src_addr/len
3338 * from the source map to the range dst_addr/len
3339 * in the destination map.
3341 * This routine is only advisory and need not do anything.
3344 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3345 vm_size_t len, vm_offset_t src_addr)
3351 * Routine: pmap_extract
3353 * Extract the physical page address associated
3354 * with the given map/virtual_address pair.
3357 pmap_extract(pmap_t pmap, vm_offset_t va)
3362 pa = pmap_extract_locked(pmap, va);
3368 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3370 struct l2_dtable *l2;
3372 pt_entry_t *ptep, pte;
3376 if (pmap != kernel_pmap)
3377 PMAP_ASSERT_LOCKED(pmap);
3379 l1pd = pmap->pm_l1->l1_kva[l1idx];
3380 if (l1pte_section_p(l1pd)) {
3382 * These should only happen for the kernel pmap.
3384 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3385 /* XXX: what to do about the bits > 32 ? */
3386 if (l1pd & L1_S_SUPERSEC)
3387 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3389 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3392 * Note that we can't rely on the validity of the L1
3393 * descriptor as an indication that a mapping exists.
3394 * We have to look it up in the L2 dtable.
3396 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3398 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3400 pte = ptep[l2pte_index(va)];
3403 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3404 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3406 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3412 * Atomically extract and hold the physical page with the given
3413 * pmap and virtual address pair if that mapping permits the given
3418 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3420 struct l2_dtable *l2;
3422 pt_entry_t *ptep, pte;
3431 l1pd = pmap->pm_l1->l1_kva[l1idx];
3432 if (l1pte_section_p(l1pd)) {
3434 * These should only happen for kernel_pmap
3436 KASSERT(pmap == kernel_pmap, ("huh"));
3437 /* XXX: what to do about the bits > 32 ? */
3438 if (l1pd & L1_S_SUPERSEC)
3439 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3441 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3442 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3443 m = PHYS_TO_VM_PAGE(pa);
3444 if (!vm_page_wire_mapped(m))
3449 * Note that we can't rely on the validity of the L1
3450 * descriptor as an indication that a mapping exists.
3451 * We have to look it up in the L2 dtable.
3453 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3456 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3461 ptep = &ptep[l2pte_index(va)];
3468 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3469 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3470 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3472 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3473 m = PHYS_TO_VM_PAGE(pa);
3474 if (!vm_page_wire_mapped(m))
3483 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
3485 struct l2_dtable *l2;
3487 pt_entry_t *ptep, pte;
3492 l1pd = kernel_pmap->pm_l1->l1_kva[l1idx];
3493 if (l1pte_section_p(l1pd)) {
3494 if (l1pd & L1_S_SUPERSEC)
3495 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3497 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3498 pte = L2_S_PROTO | pa |
3499 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
3501 l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)];
3503 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3508 pte = ptep[l2pte_index(va)];
3513 if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
3514 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3516 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3525 * Initialize a preallocated and zeroed pmap structure,
3526 * such as one in a vmspace structure.
3530 pmap_pinit(pmap_t pmap)
3532 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3534 pmap_alloc_l1(pmap);
3535 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3537 CPU_ZERO(&pmap->pm_active);
3539 TAILQ_INIT(&pmap->pm_pvlist);
3540 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3541 pmap->pm_stats.resident_count = 1;
3542 if (vector_page < KERNBASE) {
3543 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3544 VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0);
3550 /***************************************************
3551 * page management routines.
3552 ***************************************************/
3556 pmap_free_pv_entry(pv_entry_t pv)
3559 uma_zfree(pvzone, pv);
3564 * get a new pv_entry, allocating a block from the system
3566 * the memory allocation is performed bypassing the malloc code
3567 * because of the possibility of allocations at interrupt time.
3570 pmap_get_pv_entry(void)
3572 pv_entry_t ret_value;
3575 if (pv_entry_count > pv_entry_high_water)
3576 pagedaemon_wakeup(0); /* XXX ARM NUMA */
3577 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3582 * Remove the given range of addresses from the specified map.
3584 * It is assumed that the start and end are properly
3585 * rounded to the page size.
3587 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3589 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3591 struct l2_bucket *l2b;
3592 vm_offset_t next_bucket;
3595 u_int mappings, is_exec, is_refd;
3600 * we lock in the pmap => pv_head direction
3603 rw_wlock(&pvh_global_lock);
3608 * Do one L2 bucket's worth at a time.
3610 next_bucket = L2_NEXT_BUCKET(sva);
3611 if (next_bucket > eva)
3614 l2b = pmap_get_l2_bucket(pm, sva);
3620 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3623 while (sva < next_bucket) {
3632 * Nothing here, move along
3639 pm->pm_stats.resident_count--;
3645 * Update flags. In a number of circumstances,
3646 * we could cluster a lot of these and do a
3647 * number of sequential pages in one go.
3649 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3650 struct pv_entry *pve;
3652 pve = pmap_remove_pv(pg, pm, sva);
3654 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3655 is_refd = PV_BEEN_REFD(pve->pv_flags);
3656 pmap_free_pv_entry(pve);
3660 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3661 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3664 cpu_idcache_wbinv_range(sva,
3666 cpu_l2cache_wbinv_range(sva,
3668 cpu_tlb_flushID_SE(sva);
3669 } else if (is_refd) {
3670 cpu_dcache_wbinv_range(sva,
3672 cpu_l2cache_wbinv_range(sva,
3674 cpu_tlb_flushD_SE(sva);
3676 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3677 /* flushall will also only get set for
3678 * for a current pmap
3680 cpu_idcache_wbinv_all();
3681 cpu_l2cache_wbinv_all();
3694 pmap_free_l2_bucket(pm, l2b, mappings);
3697 rw_wunlock(&pvh_global_lock);
3706 * Zero a given physical page by mapping it at a page hook point.
3707 * In doing the zero page op, the page we zero is mapped cachable, as with
3708 * StrongARM accesses to non-cached pages are non-burst making writing
3709 * _any_ bulk data very slow.
3712 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3715 if (_arm_bzero && size >= _min_bzero_size &&
3716 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3721 * Hook in the page, zero it, invalidate the TLB as needed.
3723 * Note the temporary zero-page mapping must be a non-cached page in
3724 * order to work without corruption when write-allocate is enabled.
3726 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
3728 cpu_tlb_flushD_SE(cdstp);
3730 if (off || size != PAGE_SIZE)
3731 bzero((void *)(cdstp + off), size);
3739 * pmap_zero_page zeros the specified hardware page by mapping
3740 * the page into KVM and using bzero to clear its contents.
3743 pmap_zero_page(vm_page_t m)
3745 pmap_zero_page_generic(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
3750 * pmap_zero_page_area zeros the specified hardware page by mapping
3751 * the page into KVM and using bzero to clear its contents.
3753 * off and size may not cover an area beyond a single hardware page.
3756 pmap_zero_page_area(vm_page_t m, int off, int size)
3759 pmap_zero_page_generic(VM_PAGE_TO_PHYS(m), off, size);
3767 * This is a local function used to work out the best strategy to clean
3768 * a single page referenced by its entry in the PV table. It should be used by
3769 * pmap_copy_page, pmap_zero page and maybe some others later on.
3771 * Its policy is effectively:
3772 * o If there are no mappings, we don't bother doing anything with the cache.
3773 * o If there is one mapping, we clean just that page.
3774 * o If there are multiple mappings, we clean the entire cache.
3776 * So that some functions can be further optimised, it returns 0 if it didn't
3777 * clean the entire cache, or 1 if it did.
3779 * XXX One bug in this routine is that if the pv_entry has a single page
3780 * mapped at 0x00000000 a whole cache clean will be performed rather than
3781 * just the 1 page. Since this should not occur in everyday use and if it does
3782 * it will just result in not the most efficient clean for the page.
3784 * We don't yet use this function but may want to.
3787 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
3789 pmap_t pm, pm_to_clean = NULL;
3790 struct pv_entry *npv;
3791 u_int cache_needs_cleaning = 0;
3793 vm_offset_t page_to_clean = 0;
3796 /* nothing mapped in so nothing to flush */
3801 * Since we flush the cache each time we change to a different
3802 * user vmspace, we only need to flush the page if it is in the
3806 pm = vmspace_pmap(curproc->p_vmspace);
3810 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
3811 if (npv->pv_pmap == kernel_pmap || npv->pv_pmap == pm) {
3812 flags |= npv->pv_flags;
3814 * The page is mapped non-cacheable in
3815 * this map. No need to flush the cache.
3817 if (npv->pv_flags & PVF_NC) {
3819 if (cache_needs_cleaning)
3820 panic("pmap_clean_page: "
3821 "cache inconsistency");
3824 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
3826 if (cache_needs_cleaning) {
3830 page_to_clean = npv->pv_va;
3831 pm_to_clean = npv->pv_pmap;
3833 cache_needs_cleaning = 1;
3836 if (page_to_clean) {
3837 if (PV_BEEN_EXECD(flags))
3838 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
3841 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
3842 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
3843 } else if (cache_needs_cleaning) {
3844 if (PV_BEEN_EXECD(flags))
3845 pmap_idcache_wbinv_all(pm);
3847 pmap_dcache_wbinv_all(pm);
3855 * pmap_copy_page copies the specified (machine independent)
3856 * page by mapping the page into virtual memory and using
3857 * bcopy to copy the page, one machine dependent page at a
3864 * Copy one physical page into another, by mapping the pages into
3865 * hook points. The same comment regarding cachability as in
3866 * pmap_zero_page also applies here.
3869 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
3872 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
3876 * Clean the source page. Hold the source page's lock for
3877 * the duration of the copy so that no other mappings can
3878 * be created while we have a potentially aliased mapping.
3882 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
3885 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
3888 * Map the pages into the page hook points, copy them, and purge
3889 * the cache for the appropriate page. Invalidate the TLB
3893 *csrc_pte = L2_S_PROTO | src |
3894 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
3896 *cdst_pte = L2_S_PROTO | dst |
3897 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
3899 cpu_tlb_flushD_SE(csrcp);
3900 cpu_tlb_flushD_SE(cdstp);
3902 bcopy_page(csrcp, cdstp);
3904 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
3905 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
3906 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
3907 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
3911 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
3912 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
3916 *csrc_pte = L2_S_PROTO | a_phys |
3917 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
3919 *cdst_pte = L2_S_PROTO | b_phys |
3920 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
3922 cpu_tlb_flushD_SE(csrcp);
3923 cpu_tlb_flushD_SE(cdstp);
3925 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
3927 cpu_dcache_inv_range(csrcp + a_offs, cnt);
3928 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
3929 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
3930 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
3934 pmap_copy_page(vm_page_t src, vm_page_t dst)
3937 cpu_dcache_wbinv_all();
3938 cpu_l2cache_wbinv_all();
3939 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
3940 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
3941 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
3943 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
3947 * We have code to do unmapped I/O. However, it isn't quite right and
3948 * causes un-page-aligned I/O to devices to fail (most notably newfs
3949 * or fsck). We give up a little performance to not allow unmapped I/O
3950 * to gain stability.
3952 int unmapped_buf_allowed = 0;
3955 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3956 vm_offset_t b_offset, int xfersize)
3958 vm_page_t a_pg, b_pg;
3959 vm_offset_t a_pg_offset, b_pg_offset;
3962 cpu_dcache_wbinv_all();
3963 cpu_l2cache_wbinv_all();
3964 while (xfersize > 0) {
3965 a_pg = ma[a_offset >> PAGE_SHIFT];
3966 a_pg_offset = a_offset & PAGE_MASK;
3967 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3968 b_pg = mb[b_offset >> PAGE_SHIFT];
3969 b_pg_offset = b_offset & PAGE_MASK;
3970 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3971 pmap_copy_page_offs_generic(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
3972 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
3980 pmap_quick_enter_page(vm_page_t m)
3983 * Don't bother with a PCPU pageframe, since we don't support
3984 * SMP for anything pre-armv7. Use pmap_kenter() to ensure
3985 * caching is handled correctly for multiple mappings of the
3986 * same physical page.
3989 mtx_assert(&qmap_mtx, MA_NOTOWNED);
3990 mtx_lock(&qmap_mtx);
3992 pmap_kenter(qmap_addr, VM_PAGE_TO_PHYS(m));
3998 pmap_quick_remove_page(vm_offset_t addr)
4000 KASSERT(addr == qmap_addr,
4001 ("pmap_quick_remove_page: invalid address"));
4002 mtx_assert(&qmap_mtx, MA_OWNED);
4004 mtx_unlock(&qmap_mtx);
4008 * this routine returns true if a physical page resides
4009 * in the given pmap.
4012 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4018 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4019 ("pmap_page_exists_quick: page %p is not managed", m));
4021 rw_wlock(&pvh_global_lock);
4022 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4023 if (pv->pv_pmap == pmap) {
4031 rw_wunlock(&pvh_global_lock);
4036 * pmap_page_wired_mappings:
4038 * Return the number of managed mappings to the given physical page
4042 pmap_page_wired_mappings(vm_page_t m)
4048 if ((m->oflags & VPO_UNMANAGED) != 0)
4050 rw_wlock(&pvh_global_lock);
4051 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4052 if ((pv->pv_flags & PVF_WIRED) != 0)
4054 rw_wunlock(&pvh_global_lock);
4059 * This function is advisory.
4062 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4067 * pmap_ts_referenced:
4069 * Return the count of reference bits for a page, clearing all of them.
4072 pmap_ts_referenced(vm_page_t m)
4075 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4076 ("pmap_ts_referenced: page %p is not managed", m));
4077 return (pmap_clearbit(m, PVF_REF));
4082 pmap_is_modified(vm_page_t m)
4085 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4086 ("pmap_is_modified: page %p is not managed", m));
4087 if (m->md.pvh_attrs & PVF_MOD)
4095 * Clear the modify bits on the specified physical page.
4098 pmap_clear_modify(vm_page_t m)
4101 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4102 ("pmap_clear_modify: page %p is not managed", m));
4103 vm_page_assert_busied(m);
4105 if (!pmap_page_is_write_mapped(m))
4107 if (m->md.pvh_attrs & PVF_MOD)
4108 pmap_clearbit(m, PVF_MOD);
4113 * pmap_is_referenced:
4115 * Return whether or not the specified physical page was referenced
4116 * in any physical maps.
4119 pmap_is_referenced(vm_page_t m)
4122 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4123 ("pmap_is_referenced: page %p is not managed", m));
4124 return ((m->md.pvh_attrs & PVF_REF) != 0);
4129 * Clear the write and modified bits in each of the given page's mappings.
4132 pmap_remove_write(vm_page_t m)
4135 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4136 ("pmap_remove_write: page %p is not managed", m));
4137 vm_page_assert_busied(m);
4139 if (pmap_page_is_write_mapped(m))
4140 pmap_clearbit(m, PVF_WRITE);
4145 * Perform the pmap work for mincore(2). If the page is not both referenced and
4146 * modified by this pmap, returns its physical address so that the caller can
4147 * find other mappings.
4150 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
4152 struct l2_bucket *l2b;
4153 pt_entry_t *ptep, pte;
4160 l2b = pmap_get_l2_bucket(pmap, addr);
4165 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4167 if (!l2pte_valid(pte)) {
4171 val = MINCORE_INCORE;
4172 if (pte & L2_S_PROT_W)
4173 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4176 m = PHYS_TO_VM_PAGE(pa);
4177 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4181 * The ARM pmap tries to maintain a per-mapping
4182 * reference bit. The trouble is that it's kept in
4183 * the PV entry, not the PTE, so it's costly to access
4184 * here. You would need to acquire the pvh global
4185 * lock, call pmap_find_pv(), and introduce a custom
4186 * version of vm_page_pa_tryrelock() that releases and
4187 * reacquires the pvh global lock. In the end, I
4188 * doubt it's worthwhile. This may falsely report
4189 * the given address as referenced.
4191 if ((m->md.pvh_attrs & PVF_REF) != 0)
4192 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4194 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4195 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4204 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4210 * Increase the starting virtual address of the given mapping if a
4211 * different alignment might result in more superpage mappings.
4214 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4215 vm_offset_t *addr, vm_size_t size)
4219 #define BOOTSTRAP_DEBUG
4224 * Create a single section mapping.
4227 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4228 int prot, int cache)
4230 pd_entry_t *pde = (pd_entry_t *) l1pt;
4233 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4242 fl = pte_l1_s_cache_mode;
4246 fl = pte_l1_s_cache_mode_pt;
4250 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4251 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4252 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4259 * Link the L2 page table specified by l2pv.pv_pa into the L1
4260 * page table at the slot for "va".
4263 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4265 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4266 u_int slot = va >> L1_S_SHIFT;
4268 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4270 #ifdef VERBOSE_INIT_ARM
4271 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4274 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4276 PTE_SYNC(&pde[slot]);
4278 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4286 * Create a single page mapping.
4289 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4292 pd_entry_t *pde = (pd_entry_t *) l1pt;
4296 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4305 fl = pte_l2_s_cache_mode;
4309 fl = pte_l2_s_cache_mode_pt;
4313 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4314 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4316 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4319 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4321 pte[l2pte_index(va)] =
4322 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4323 PTE_SYNC(&pte[l2pte_index(va)]);
4329 * Map a chunk of memory using the most efficient mappings
4330 * possible (section. large page, small page) into the
4331 * provided L1 and L2 tables at the specified virtual address.
4334 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4335 vm_size_t size, int prot, int cache)
4337 pd_entry_t *pde = (pd_entry_t *) l1pt;
4338 pt_entry_t *pte, f1, f2s, f2l;
4342 resid = roundup2(size, PAGE_SIZE);
4345 panic("pmap_map_chunk: no L1 table provided");
4347 #ifdef VERBOSE_INIT_ARM
4348 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4349 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4361 f1 = pte_l1_s_cache_mode;
4362 f2l = pte_l2_l_cache_mode;
4363 f2s = pte_l2_s_cache_mode;
4367 f1 = pte_l1_s_cache_mode_pt;
4368 f2l = pte_l2_l_cache_mode_pt;
4369 f2s = pte_l2_s_cache_mode_pt;
4376 /* See if we can use a section mapping. */
4377 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4378 #ifdef VERBOSE_INIT_ARM
4381 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4382 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4383 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4384 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4392 * Ok, we're going to use an L2 table. Make sure
4393 * one is actually in the corresponding L1 slot
4394 * for the current VA.
4396 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4397 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4399 pte = (pt_entry_t *) kernel_pt_lookup(
4400 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4402 panic("pmap_map_chunk: can't find L2 table for VA"
4404 /* See if we can use a L2 large page mapping. */
4405 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4406 #ifdef VERBOSE_INIT_ARM
4409 for (i = 0; i < 16; i++) {
4410 pte[l2pte_index(va) + i] =
4412 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4413 PTE_SYNC(&pte[l2pte_index(va) + i]);
4421 /* Use a small page mapping. */
4422 #ifdef VERBOSE_INIT_ARM
4425 pte[l2pte_index(va)] =
4426 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4427 PTE_SYNC(&pte[l2pte_index(va)]);
4432 #ifdef VERBOSE_INIT_ARM
4440 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4443 * Remember the memattr in a field that gets used to set the appropriate
4444 * bits in the PTEs as mappings are established.
4446 m->md.pv_memattr = ma;
4449 * It appears that this function can only be called before any mappings
4450 * for the page are established on ARM. If this ever changes, this code
4451 * will need to walk the pv_list and make each of the existing mappings
4452 * uncacheable, being careful to sync caches and PTEs (and maybe
4453 * invalidate TLB?) for any current mapping it modifies.
4455 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
4456 panic("Can't change memattr on page with existing mappings");
4460 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
4463 return (mode == VM_MEMATTR_DEFAULT || mode == VM_MEMATTR_UNCACHEABLE);